초록 ▼

A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. T

A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues. Data ensuing from the request can be re-ordered and presented to the destination based on the current pointer position within the in-order queue. Thus, the in-order queue keeps track of the order in which data is transferred across the processor bus consistent with the order in which the previous requests were transferred.

대표청구항 ▼

[What is claimed is:] [1.]a processor controller having both a memory request queue and a peripheral request queue for storing respective memory requests and peripheral requests dispatched from a processor operably linked to the processor controller; anda peripheral device coupled to receive the per

[What is claimed is:] [1.]a processor controller having both a memory request queue and a peripheral request queue for storing respective memory requests and peripheral requests dispatched from a processor operably linked to the processor controller; anda peripheral device coupled to receive the peripheral requests, wherein the peripheral device is arranged exclusive of a printed circuit board on which the processor controller is configured.