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A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory co

A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

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[What is claimed is:] [1.](a) selecting a first set of data bits to be placed on the system memory bus;(b) transferring a first half of the data bits selected in step (a) onto the host bus, the transfer being done directly from the system memory bus to the host bus without transmission through a mem

[What is claimed is:] [1.](a) selecting a first set of data bits to be placed on the system memory bus;(b) transferring a first half of the data bits selected in step (a) onto the host bus, the transfer being done directly from the system memory bus to the host bus without transmission through a memory control unit;(c) transferring a second half of the data bits selected in step (a) onto the host bus, the transfer being done directly from the system memory bus to the host bus without transmission through a memory control unit;(d) selecting a second set of data bits to be placed on the memory bus;(e) transferring a first half of the data bits selected in step (d) onto the host bus, the transfer being done directly from the system memory bus to the host bus without transmission through a memory control unit;(f) transferring a second half of the data bits selected in step (d) onto the host bus, the transfer being done directly from the system memory bus to the host bus without transmission through a memory control unit.