초록 ▼

A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches data elements of a vector into the first memo

A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches data elements of a vector into the first memory prior to processing such data elements. If a requested data element is not present in the first memory, a load request is issued to the second memory and to lower levels of the memory hierarchy until the requested data element is finally retrieved and stored in the first memory. The data processor (10) continues to prefetch subsequent data elements of the vector by considering the length of the data element and the stride of the vector. In one embodiment, the data processor (10) prefetches the vector into the first memory in response to a single data stream touch load (DST) instruction (100).

대표청구항 ▼

[We claim:] [1.]a first register for storing n;a second register for storing s;a third register for storing ea;an arithmetic unit having a first input coupled to the second register, a second input coupled to the third register, and an output terminal, for calculating the effective address ea of eac

[We claim:] [1.]a first register for storing n;a second register for storing s;a third register for storing ea;an arithmetic unit having a first input coupled to the second register, a second input coupled to the third register, and an output terminal, for calculating the effective address ea of each unit i of the n units of the vector and for providing a fetch address to the output terminal thereof corresponding to the effective address ea when enabled;a load unit coupled to the first memory and to the second memory and having an input terminal for receiving the fetch address, for prefetching a data element located at the fetch address from the second memory into the first memory; anda state machine having an input coupled to the first register, for enabling the arithmetic unit in response to the data processor receiving a predetermined instruction, and for enabling the arithmetic unit repetitively until an nth unit of the vector has been prefetched.