|국가/구분||United States(US) Patent 등록|
|미국특허분류(USC)||711/137 ; 712/006|
|발명자 / 주소|
|출원인 / 주소|
|대리인 / 주소||
|인용정보||피인용 횟수 : 98 인용 특허 : 5|
A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches data elements of a vector into the first memory prior to processing such data elements. If a requested data element is not present in the first memory, a load request is issued to the second memory and to lower levels of the memory hierarchy until the requested data element is finally retrieved and store...
[We claim:] [1.]a first register for storing n;a second register for storing s;a third register for storing ea;an arithmetic unit having a first input coupled to the second register, a second input coupled to the third register, and an output terminal, for calculating the effective address ea of each unit i of the n units of the vector and for providing a fetch address to the output terminal thereof corresponding to the effective address ea when enabled;a load unit coupled to the first memory and to the second memory and having an input terminal for rece...