초록 ▼

Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present inventio

Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

대표청구항 ▼

[What is claimed is:] [1.]a memory array having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at points of intersection thereof;a control circuit coupled to said memory array via a plurality of first signal lines;a processing circuit coupled to said co

[What is claimed is:] [1.]a memory array having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at points of intersection thereof;a control circuit coupled to said memory array via a plurality of first signal lines;a processing circuit coupled to said control circuit via a plurality of second signal lines;an input/output circuit coupled to said control circuit via a third signal line, anda control node to which a control signal is input,wherein the semiconductor integrated circuit device is formed on a chip,wherein said control circuit has a switching circuit for selectively connecting one of the first signal lines to the third signal line,wherein the control signal is supplied from outside of the chip, andwherein said processing circuit can be disabled based on the control signal.