초록 ▼

An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited

An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited copper metal plug. An encapsulating metal deposit caps the plug without any intervening oxidation and degradation. In a transition from copper to a codeposit of copper, an encapsulating Pt, Pd, and/or Ag metal deposits in the electroless bath without oxidation and degradation followed by a pure deposit of the encapsulating metal layer to cap the plug. The surface of the encapsulating metal deposit is formed by overgrowth above the plug hole followed by polishing the surface of the insulator layer removing the overgrowth of the metal layer polished by a CMP process to planarize the surface of the insulator layer which is the top surface of device to achieve coplanarity of metal layer with the topography of the insulator layer.

대표청구항 ▼

[ Having thus described the invention, what is claimed as new and desirable to be secured by Letters Patent is as follows:] [1.]1. A method of forming a copper plug on a doped silicon semiconductor substrate having a substrate surface which is covered with an insulation layer in the sequence of step

[ Having thus described the invention, what is claimed as new and desirable to be secured by Letters Patent is as follows:] [1.]1. A method of forming a copper plug on a doped silicon semiconductor substrate having a substrate surface which is covered with an insulation layer in the sequence of steps comprising:forming a plug hole in the insulation layer down to the doped silicon substrate surface, the plug hole having walls, a top and a bottom comprising a portion of the substrate surface, the plug hole having a hole depth,then forming a metal diffusion barrier on the walls and the bottom of in the hole on the doped silicon substrate surface,partially filling the plug hole with a copper metal deposit to a predetermined plug depth as a plug wherein the plug depth is less than the hole depth of the hole leaving a space in the plug hole above the copper metal deposit,depositing an encapsulating metal layer composed of a metal other than copper on the surface of the copper metal deposit including an overgrowth above the plug hole capping the plug and thereby filling the space in the plug hole, andthen polishing the surface ofthe insulator layer removing the overgrowth of the metal layer to planarize the surface of the insulator layer which is the top surface of device to achieve coplanarity of metal layer with the topography of the insulator layer.