초록 ▼

A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The recon

A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator.

대표청구항 ▼

[ What is claimed is:] [3.]3. A method of generating disparity results with low latency in a data processing system that processes elements of a first data set and a second data set, each having a plurality of elements, comprising:receiving elements of the first and second data sets, including a fir

[ What is claimed is:] [3.]3. A method of generating disparity results with low latency in a data processing system that processes elements of a first data set and a second data set, each having a plurality of elements, comprising:receiving elements of the first and second data sets, including a first element of the first data set that is offset from each of a plurality of selected elements of the second data set by a particular disparity;performing transformations on such received elements, including the first element and each of the plurality of selected elements; andcorrelating the transformed first element with each of the plurality of transformed selected elements to generate a correlation result for each disparity, while concurrently performing transformations on one or more elements of each of the first and second data sets.