초록 ▼

Techniques for scaling of a model design to provide a scaled design are described whereby parameters of a model design such as size, circuit complexity, interconnection density, number of I/O connections, etc., can be scaled to produce a scaled version of the design. The scaling techniques employ mu

Techniques for scaling of a model design to provide a scaled design are described whereby parameters of a model design such as size, circuit complexity, interconnection density, number of I/O connections, etc., can be scaled to produce a scaled version of the design. The scaling techniques employ multi-level hierarchical module replication to produce fully-functional scaled designs which closely match the function of the model design. Test vectors for the scaled designs can be readily obtained by altering test vectors for the model design to account for the replicated modules.

대표청구항 ▼

[ What is claimed is:] [1.]1. A method for creating a physical circuit design from a high-level design, comprising the steps of:planning an initial design for a plurality of hierarchical entities according to a predetermined set of design constraints;revising the initial design by apportioning place

[ What is claimed is:] [1.]1. A method for creating a physical circuit design from a high-level design, comprising the steps of:planning an initial design for a plurality of hierarchical entities according to a predetermined set of design constraints;revising the initial design by apportioning placement and wiring resources among different hierarchical entities;estimating the area required for planning areas of the physical design;generating an area plan based on design revisions;interactively altering said area plan to conform with predetermined system goals;specifying a desired behavior for said circuit design;interactively simulating and changing said circuit design until said predetermined set of design constraints is achieved;partitioning the design into said hierarchical entities;directing the hierarchical entities to a logic synthesis program;providing a set of scaling parameters on parameters of said circuit design, wherein the step of planning said initial design for said plurality of hierarchical entities further comprises repeating and interconnecting said circuit design thereby producing a fully-functional, scaled design satisfying predetermined scaling constraints;providing test vectors for said circuit design and hierarchical entities of said circuit design; andproviding test vectors for the scaled design based on the test vectors of the design blocks, wherein at least one scaling parameter relates to interconnection density, wherein at least one constraint relates to the number of I/O connection points.