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Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/20
출원번호 US-0036356 (1998-03-06)
우선권정보 KR0048930 (1997-09-26)
발명자 / 주소
  • Lee Seung-Hwan,KRX
  • Lee Sang-Hyeop,KRX
  • Kim Young-Sun,KRX
  • Shim Se-Jin,KRX
  • Jin You-Chan,KRX
  • Moon Ju-Tae,KRX
  • Choi Jin-Seok,KRX
  • Kim Young-Min,KRX
  • Kim Kyung-Hoon,KRX
  • Nam Kab-Jin,KRX
  • Par
출원인 / 주소
  • Samsung Electronics Co., Ltd., KRX
대리인 / 주소
    Myers Bigel Sibley & Sajovec
인용정보 피인용 횟수 : 51  인용 특허 : 56

초록 ▼

Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the

대표청구항 ▼

[ That which is claimed is:] [1.]1. A method of forming an integrated circuit capacitor, comprising the steps of:forming a conductive layer pattern on a semiconductor substrate;forming a hemispherical grain (HSG) silicon surface layer having first conductivity type dopants therein, on the conductive

이 특허에 인용된 특허 (56)

  1. Mathews Viju K. (Boise ID), Barrier process for Ta2O5 capacitor.
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  2. Lee Young Jong,KRX, Capacitor structure for semiconductor device and method of manufacturing the same.
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  3. Reinberg Alan R. (Westport CT) Tuttle Mark E. (Boise ID), Dram cell having a stacked capacitor with a tantalum lower plate, a tantalum oxide dielectric layer, and a silicide buri.
    상세보기
  4. Harshfield Steven T. (Emmett ID), Hemispherical grained silicon on refractory metal nitride.
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  5. Yoo Cha-young (Kyungki-do KRX) Kim Young-sun (Kyungki-do KRX) Park Young-wook (Kyungki-do KRX) Shim Se-jin (Kyungki-do KRX), High capacitance capacitor manufacturing method.
    상세보기
  6. Lou Chine-Gie (Hsinchu TWX) Lee Yu-Hua (Hsinchu TWX), Increased surface area for DRAM, storage node capacitors, using a novel polysilicon deposition and anneal process.
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  7. Chiba Atsushi (Tokyo JPX), Manufacturing method for semiconductor memories.
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  8. Ahn Ji-hong (Seoul KRX), Manufacturing method of a capacitor having a storage electrode whose sidewall is positively inclined with respect to the.
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  9. Ryou Eui K. (Kyoungki KRX), Method for fabricating a stacked capacitor cell in semiconductor memory device.
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  10. Koh Chao-Ming (Hsinchu TWX), Method for fabricating a stacked capacitor with a self aligned node contact in a memory cell.
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  11. Tanigawa Takaho (Tokyo JPX), Method for fabricating capacitive element of semiconductor memory device.
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  12. Cho Bok-Won,KRX, Method for fabricating capacitor of semiconductor device using hemispherical grain (HSG) polysilicon.
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  13. Tseng Horng-Huei,TWX ; Lu Chih-Yuan,TWX, Method for forming a DRAM capacitor using HSG-Si.
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  14. Cheng Chih-Hsiung,TWX, Method for forming a capacitor using a hemispherical-grain structure.
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  15. Ping Er-Xuan ; Thakur Randhir P. S., Method for forming controllable surface enhanced three dimensional objects.
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  16. Weimer Ronald A. (Boise ID) Thakur Randhir P. S. (Boise ID) Kepten Avishai (Migdal Haemek ILX) Sendler Michael (Migdal Haemek ILX), Method for forming hemispherical grained silicon.
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  17. Yew Tri-Rung,TWX ; Lur Water,TWX ; Sun Shih-Wei,TWX, Method for growing hemispherical grain silicon.
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  18. Figura Thomas A., Method for increasing capacitance of an HSG rugged capacitor using a phosphine rich oxidation and subsequent wet etch.
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  19. Figura Thomas A. (Boise ID), Method for increasing capacitance of an HSG rugged capacitor using a phosphine rich oxidation and subsequent wet etch.
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  20. Ahn Ji-hong (Seoul KRX) Seo Young-woo (Kyungsangbak-do KRX), Method for manufacturing a capacitor of an integrated semiconductor device having increased surface area.
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  21. Kamiyama Satoshi (Tokyo JPX), Method for manufacturing a semiconductor device.
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  22. Park Young-woo (Kyungi-do KRX) No Jun-yong (Incheon KRX) Sim Sang-pil (Suwon KRX), Method for manufacturing a semiconductor memory device having a capacitor with increased effective area.
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  23. Ryou Eui K. (Ichonkun KRX), Method for the fabrication of capacitor in semiconductor device.
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  24. Turner Charles ; Thakur Randhir P. S., Method for uniformly doping hemispherical grain polycrystalline silicon.
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  25. Crenshaw Darius Lammont ; Wise Rick L. ; McKee Jeffrey, Method of fabricating a dynamic random access memory (DRAM) cell capacitor using hemispherical grain (HSG) polysilicon.
    상세보기
  26. Tsai Hong-Hsiang,TWX, Method of fabricating capacitor over bit line COB structure for a very high density DRAM applications.
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  27. Harshfield Steven T., Method of forming a hemispherical grained silicon on refractory metal nitride.
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  28. Weimer Ronald A. ; Thakur Randhir P. S. ; Kepten Avishai,ILX ; Sendler Michael,ILX, Method of forming hemispherical grained silicon.
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  29. Mathews Viju (Boise ID) Turner Charles (Boise ID), Method of increasing capacitance of polycrystalline silicon devices by surface roughening and polycrystalline silicon de.
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  30. Kim Kyung-hoon,KRX ; Park Young-wook,KRX ; Yoo Cha-young,KRX, Method of making capacitor of highly integrated semiconductor device using multiple insulation layers.
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  31. Kim Sung-tae (Seoul KRX) Lee Hyeung-gyu (Seoul KRX) Ko Jae-hong (Seoul KRX), Method of making semiconductor device having a capacitor of large capacitance.
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  32. Lin Dahcheng,TWX ; Chang Jung-Ho,TWX ; Chen Hsi-Chuan,TWX, Method of manufacturing hemispherical grained polysilicon with improved adhesion and reduced capacitance depletion.
    상세보기
  33. Tatsumi Toru (Tokyo JPX) Sakai Akira (Tokyo JPX), Method of manufacturing polysilicon film including recrystallization of an amorphous film.
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  34. Lowrey Tyler A. ; Schuegraf Klaus F. ; Thakur Randhir P. S., Method of monitoring a process of manufacturing a semiconductor wafer including hemispherical grain polysilicon.
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  35. Zenke Masanobu,JPX, Method of roughening a polysilicon layer of a random crystal structure included in a semiconductor device.
    상세보기
  36. Thakur Randhir P. S. (Boise ID) Breiner Lyle D. (Boise ID), Method to form hemi-spherical grain (HSG) silicon from amorphous silicon.
    상세보기
  37. Thakur Randhir P. S. (Boise ID) Nuttall Michael (Meridian ID), Method to form hemispherical grain (HSG) silicon by implant seeding followed by vacuum anneal.
    상세보기
  38. Cherng George Meng-Jaw,TWX, Method to improve yield for capacitors formed using etchback of polysilicon hemispherical grains.
    상세보기
  39. Thakur Randhir P. S. (Boise ID), Method to prepare hemi-spherical grain (HSG) silicon using a fluorine based gas mixture and high vacuum anneal.
    상세보기
  40. Thakur Randhir P. S. (Boise ID), Method to prepare hemi-spherical grain (HSG) silicon using a fluorine based gas mixture and high vacuum anneal.
    상세보기
  41. Dennison Charles H. (Meridian ID) Thakur Randhir P. S. (Boise ID), Method to thermally form hemispherical grain (HSG) silicon to enhance capacitance for application in high density DRAMs.
    상세보기
  42. Han Chan-hee,KRX ; Yang Chang-jip,KRX ; Park Young-kyou,KRX ; Kim Jae-wook,KRX, Methods of forming hemispherical grained silicon electrodes including multiple temperature steps.
    상세보기
  43. Shin Hyun-bo,KRX ; Kim Jong-young,KRX, Methods of forming hemispherical grained silicon layers including anti-nucleation gases.
    상세보기
  44. Mathews Viju K. ; Jeng Nanseng ; Fazan Pierre, Process for doping hemispherical grain silicon.
    상세보기
  45. Kamiyama Satoshi (Tokyo JPX), Process for manufacturing semiconductor device.
    상세보기
  46. Lou Chine-Gie (Hsinchu TWX), Process for producing a stacked capacitor having polysilicon with optimum hemispherical grains.
    상세보기
  47. Fazan Pierre (Boise ID) Mathews Viju (Boise ID), Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node.
    상세보기
  48. Nishioka Yasushiro (Hachioji JPX) Homma Noriyuki (Kokubunji JPX) Sakuma Noriyuki (Hachioji JPX) Mukai Kiichiro (Hachioji JPX), Semiconductor device.
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  49. Kim Sung-tae (Seoul KRX) Lee Hyeung-gyu (Seoul KRX) Ko Jae-hong (Seoul KRX), Semiconductor device having a capacitor with an electrode grown through pinholes.
    상세보기
  50. Watanabe Hirohito (Tokyo JPX) Tatsumi Toru (Tokyo JPX), Semiconductor device having polycrystalline silicon layer with uneven surface defined by hemispherical or mushroom like.
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  51. Okudaira Tomonori (Hyogo JPX) Kashihara Keiichiro (Hyogo JPX), Semiconductor device high dielectric capacitor with narrow contact hole.
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  52. Ping Er-Xang (Boise ID) Thakur Randhir P. S. (Boise ID), Semiconductor processing method of making a hemispherical grain (HSG) polysilicon layer.
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  53. Zahurak John K. (Boise ID) Schuegraf Klaus F. (Boise ID) Thakur Randhir P. S. (Boise ID), Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon.
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  54. Brown Kris K. (Garden City ID), Storage capacitor structures using CVD tin on hemispherical grain silicon.
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  55. Emesh Ismail T. (Cumberland CAX) Calder Iain D. (Kanata CAX) Ho Vu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Madsen Lynnette D. (Ottawa CAX), Structure and method of making a capacitor for an intergrated circuit.
    상세보기
  56. Lu Chih-Yuan,TWX ; Tseng Horng-Huei,TWX, method for forming a DRAM capacitor using HSG-Si technique and oxygen implant.
    상세보기

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  2. Moradi, Behnam; Ping, Er-Xuan; Zheng, Lingyi A.; Packard, John, Capacitor constructions comprising a nitrogen-containing layer over a rugged polysilicon layer.
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  7. Derderian,Garo J.; Sandhu,Gurtej S., Capacitor fabrication methods including forming a conductive layer.
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  9. Lee, Kee Jeung; Kim, Dong Jun, Capacitor for semiconductor memory device and method of manufacturing the same.
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  10. Tang,Sanh D.; Cho,Chih Chen; Burke,Robert; Iyengar,Anuradha; Gifford,Eugene R., Cross diffusion barrier layer in polysilicon.
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  11. Tang,Sanh D.; Cho,Chih Chen; Burke,Robert; Iyengar,Anuradha; Gifford,Eugene R., Cross diffusion barrier layer in polysilicon.
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  12. Al-Shareef, Husam N.; DeBoer, Scott; Thakur, Randhir, Double layer electrode and barrier system on hemispherical grain silicon for use with high dielectric constant materials and methods for fabricating the same.
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  13. Husam N. Al-Shareef JO; Scott DeBoer ; Randhir Thakur, Double layer electrode and barrier system on hemispherical grain silicon for use with high dielectric constant materials and methods for fabricating the same.
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  14. Agarwal,Vishnu K.; Mercaldi,Garry A., Enhanced surface area capacitor fabrication methods.
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  15. Derderian,Garo J.; Sandhu,Gurtej S., Enhanced surface area capacitor fabrication methods.
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  20. Beeman, Donald St. John; Werking, Paul M., Low cost bias technique for dual plate integrated capacitors.
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  25. Don Carl Powell ; Garry Anthony Mercaldi ; Ronald A. Weimer, Method for forming a barrier layer.
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  26. Nomura, Hisashi; Takasawa, Yushin; Karasawa, Hajime; Imai, Yoshinori; Yoshida, Tadanori; Yamaguchi, Kenichi, Method for manufacturing semiconductor device, substrate treatment method, and semiconductor manufacturing apparatus.
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  31. Mohamed el-Hamdi ; Sam E. Sawaya ; Scott Balfour ; Louay M. Semaan, Methods of fabricating a memory device.
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  33. Park, Ki-yeon; Park, Heung-soo; Park, Young-wook, Methods of fabricating capacitors including Ta2O5 layers in a chamber including changing a Ta2O5 layer to heater separation or chamber pressure.
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  38. Yoo, Cha-young; Lim, Han-jin; Kim, Wan-don; Lee, Se-jin; Park, Soon-yeon; Jeong, Yong-kuk; Choi, Han-mei; Hong, Gyung-hoon; Won, Seok-jun, Methods of forming multilayer dielectric regions using varied deposition parameters.
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  40. el-Hamdi, Mohamed; Phan, Tony T.; Hendrix, Luther; Moore, Bradley T., Methods to improve density and uniformity of hemispherical grain silicon layers.
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