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Planarization of non-planar surfaces in device fabrication 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/311
출원번호 US-0177019 (1998-10-22)
발명자 / 주소
  • Marsh Eugene P.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Trask Britt
인용정보 피인용 횟수 : 147  인용 특허 : 40

초록

A method of planarizing a surface of a wafer includes providing a planarization material on the wafer surface and bringing a substantially flat surface into contact with the planarization material on the wafer. The planarization material is exposed to radiation at a first wavelength to cure the plan

대표청구항

[ What is claimed is:] [1.]1. A method of planarizing a surface of a wafer, the method comprising:providing a planarization material on the wafer surface;bringing a substantially flat surface into contact with the planarization material on the wafer surface;exposing the planarization material to rad

이 특허에 인용된 특허 (40)

  1. Choinski Edward J. (Wayland MA), Apparatus and method for temporarily sealing holes in printed circuit boards.
  2. Kishii Sadahiro (Kawasaki JPX) Arimoto Yoshihiro (Kawasaki JPX), Apparatus and method for uniformly polishing a wafer.
  3. Inselmann Jrgen (Lhne DEX), Apparatus for bonding textile sheet-like structures.
  4. Shendon Norman (San Carlos CA), Chemical mechanical polishing apparatus with improved carrier and method of use.
  5. Shimomura Mariko (Yokohama JPX) Miyashita Naoto (Yokohama JPX) Ohashi Hiroyuki (Kamakura JPX), Chemical-mechanical polishing (CMP) method for controlling polishing rate using ionized water, and CMP apparatus.
  6. Chen Lai-Juh (Hsin-Chu TWX), Chemical/mechanical polish (CMP) thickness monitor.
  7. Bunch Jesse C. (Silver Spring MD), Cube press.
  8. Prybyla Judith Ann ; Taylor Gary Newton, Device fabrication involving planarization.
  9. Weling Milind G. (San Jose CA) Bothra Subhas (San Jose CA) Gabriel Calvin T. (Cupertino CA), Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing.
  10. Miyashita Akimi (Toride JPX) Fujii Mutsumasa (Ibaraki-ken JPX) Mishina Haruo (Ushiku JPX), Hot press with pressure vessels to uniformly distribute pressure to the work piece.
  11. Sandhu Gurtej S. (Boise ID) Yu Chris C. (Austin TX), IC chemical mechanical planarization process incorporating slurry temperature control.
  12. Lee Ruojia (Boise ID) Gonzalez Fernando (Boise ID), Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance.
  13. Lee Ruojia (Boise ID) Gonzalez Fernando (Boise ID), Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance.
  14. Yu Chris C. (Boise ID) Sandhu Gurtej S. (Boise ID) Doan Trung T. (Boise ID), Integrated circuit polishing method.
  15. Chou Richard Tien-Hua (Wilmington DE), Ionomers based on copolymers of ethylene with both mono-and dicarboxylic acids.
  16. Tuttle Mark E. (Boise ID) Doan Trung T. (Boise ID) Fox Angus C. (Boise ID) Sandhu Gurtej S. (Boise ID) Stroupe Hugh E. (Boise ID), Method and apparatus for improving planarity of chemical-mechanical planarization operations.
  17. Hamamura Fumio (Kanagawa JPX) Oka Yukio (Yamaguchi JPX), Method and apparatus for pressure sticking a thin film to a base plate.
  18. Reavill Joseph A. (Mira Loma CA) Arachi John M. (Riverside CA), Method and apparatus for vacuum lamination of flex circuits.
  19. Tsunoda Kazuyoshi (Yuki JPX) Tonoki Kenji (Yuki JPX) Yokono Haruki (Yuki JPX) Kono Hisao (Yuki JPX) Yokoyama Ryoji (Musashino JPX) Kobayashi Kazuo (Shimodate JPX), Method and device for manufacturing a laminated material.
  20. Paranjpe Ajit P. (Plano TX), Method for planarization.
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  22. Hayashi Yoshihiro (Tokyo JPX), Method of flattening the surface of a semiconductor device by polishing.
  23. Blalock Guy (Boise ID) Wald Phillip G. (Boise ID), Method of forming a stacked capacitor with striated electrode.
  24. Tola Jeffry (Morrison IL), Method of making diaphragm-type pressure transducers.
  25. Matsuda Tetsuo (Poughkeepsie NY) Okumura Katsuya (Poughkeepsie NY), Method of planarizing a semiconductor workpiece surface.
  26. Schwarzbauer Herbert (Munich DEX), Method of securing electronic components to a substrate.
  27. Doan Trung T. (Boise ID) Yu Chris C. (Boise ID), Multiple step method of chemical-mechanical polishing which minimizes dishing.
  28. Kudo Takanori (Sayama JPX) Masuda Seiya (Tokorozawa JPX) Kinoshita Yoshiaki (Tokyo JPX) Przybilla Klaus (Frankfurt DEX) Endo Natsumi (Kawagoe JPX) Suehiro Natsumi (Kawagoe JPX) Okazaki Hiroshi (Kawag, Pattern forming material including photoacid and photobase generators for large exposure latitude.
  29. Stroupe Hugh (Boise ID) Sharan Sujit (Boise ID) Sandhu Gurtej S. (Boise ID), Polishing apparatus, a polishing wafer carrier apparatus, a replacable component for a particular polishing apparatus an.
  30. Katakabe Ichiro (Kanagawa-ken JPX) Miyashita Naoto (Kanagawa-ken JPX) Akiyama Tatsuo (Tokyo JPX), Polishing method and apparatus for detecting a polishing end point of a semiconductor wafer.
  31. Robinson Karl M. (Boise ID), Polishing pad and a method for making a polishing pad with covalently bonded particles.
  32. Talieh Homayoun (San Jose CA) Weldon David E. (Los Gatos CA), Polishing pad cluster for polishing a semiconductor wafer.
  33. Karlsrud Chris (Chandler AZ), Polishing pad conditioning.
  34. Winkle Mark Robert (Lansdale PA), Positive acting photoresist comprising a photoacid, a photobase and a film forming acid-hardening resin system.
  35. Namysl Edmond (1907 Frederick Placentia CA 92670), Printed circuit board laminating machine.
  36. Jacob Adir (23 Juniper La. Framingham MA 01701), Process for dry sterilization of medical devices and materials.
  37. Blalock Guy (Boise ID) Wald Phillip G. (Boise ID), Stacked capacitor construction.
  38. Iijima Nobuo (Kawasaki JPX) Hayashida Akihisa (Kawasaki JPX), Tape-on-wafer mounting apparatus and method.
  39. Pasch Nicholas F. (Pacifica CA) Mallon Thomas G. (Santa Clara CA) Franklin Mark A. (Scott\s Valley CA), Techniques for assembling polishing pads for chemi-mechanical polishing of silicon wafers.
  40. Clover Richmond B. (1199 W. Vanderbilt Ct. Sunnyvale CA 94087), Vertically stacked planarization machine.

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