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Circuit arrangement and method of dispatching instructions to multiple execution units 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/28
  • G06F-009/22
출원번호 US-0179603 (1998-10-27)
발명자 / 주소
  • Lipasti Mikko Herman
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Stinebruner
인용정보 피인용 횟수 : 67  인용 특허 : 2

초록

A data processing system, circuit arrangement, integrated circuit device, program product, and method dispatch multiple copies of a producer instruction to multiple execution units in a processor whenever it is determined that the producer instruction has or is likely to have multiple consumer instr

대표청구항

[ What is claimed is:] [1.]1. A circuit arrangement, comprising:(a) a plurality of execution units, each execution unit configured to execute instructions supplied thereto; and(b) a dispatch unit, coupled to the plurality of execution units, the dispatch unit configured to determine whether to dispa

이 특허에 인용된 특허 (2)

  1. Kogge Peter M. (Endicott NY), Dynamic multi-mode parallel processing array.
  2. Sharangpani Harshvardhan P. (Santa Clara CA) Fielden Kent G. (Sunnyvale CA) Mulder Hans J. (San Francisco CA), Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions.

이 특허를 인용한 특허 (67)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  11. Seong,Nak hee; Lim,Kyoung mook; Jeong,Seh woong; Park,Jae hong; Im,Hyung jun; Bae,Gun young; Kim,Young duck, Apparatus and method for dispatching very long instruction word having variable length.
  12. Swoboda, Gary L., Apparatus and method for processor power measurement in a digital signal processor using trace data and simulation techniques.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  17. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  18. Ando,Hideki; Shimada,Hajime; Mochizuki,Atsushi, Clustered superscalar processor with communication control between clusters.
  19. Nemirovsky,Mario; Melvin,Stephen W.; Sampath,Nandakumar; Musoll,Enrique; Urdaneta,Hector, Clustering stream and/or instruction queues for multi-streaming processors.
  20. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  21. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  22. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  23. Lindholm, John Erik; Wierzbicki, Jered, Dispatching of instructions for execution by heterogeneous processing engines.
  24. Mills, Peter C.; Oberman, Stuart F.; Lindholm, John Erik; Liu, Samuel, Dynamic load balancing of instructions for execution by heterogeneous processing engines.
  25. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  26. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  27. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  28. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  29. Nemirovsky,Mario; Nemirovsky,Adolfo; Sankar,Narendra; Musoll,Enrique, Fetch and dispatch disassociation apparatus for multi-streaming processors.
  30. Nemirovsky, Mario D.; Nemirovsky, Adolfo M.; Sankar, Narendra; Musoll, Enrique, Fetch and dispatch disassociation apparatus for multistreaming processors.
  31. Nemirovsky,Mario; Nemirovsky,Adolfo; Sankar,Narendra; Musoll,Enrique, Fetch and dispatch disassociation apparatus for multistreaming processors.
  32. Frank, Steven; Imai, Shigeki, General purpose embedded processor.
  33. Frank, Steven; Imai, Shigeki, General purpose embedded processor.
  34. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  35. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  36. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  37. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  38. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  39. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  40. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  41. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  42. Jourdan,Stephan J.; Sodani,Avinash; Farcy,Alexandre J.; Hammarlund,Per; Hily,Sebastien; Davis,Mark C., Method and apparatus for microarchitecture partitioning of execution clusters.
  43. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  44. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  45. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  46. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  47. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  48. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  49. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  50. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  51. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  52. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  53. Pestoni,Florian, Method for processing a request to multiple instances of a server program.
  54. Eder,Stefan; Fenzl,Gunther, Method for setting up a program-controlled circuit arrangement and circuit arrangement for execution of the method.
  55. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  56. Lutz, David Raymond, Pipe scheduling for pipelines based on destination register number.
  57. Sheaffer, Gad S., Pre-steering register renamed instructions to execution unit associated locations in instruction cache.
  58. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  59. Cantin, Jason F.; Kunkel, Steven R., Shared data prefetching with memory region cache line monitoring.
  60. Master,Paul L.; Watson,John, Storage and delivery of device features.
  61. Golla, Robert T.; Grohoski, Gregory F., System and method for balancing instruction loads between multiple execution units using assignment history.
  62. Sperber,Zeev; Anati,Ittai; Liron,Oded; Abdallah,Mohammad, System and method of converting data formats and communicating between execution units.
  63. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  64. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  65. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  66. Frank, Steven; Imai, Shigeki; Yoneda, Terumasa, Virtual processor methods and apparatus with unified event notification and consumer-producer memory operations.
  67. Frank, Steven; Imai, Shigeki; Yoneda, Terumasa, Virtual processor methods and apparatus with unified event notification and consumer-producer memory operations.
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