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[미국특허] Flip-chip having an on-chip decoupling capacitor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/02
  • H05K-001/16
  • H01K-023/48
출원번호 US-0227594 (1999-01-08)
발명자 / 주소
  • Mak Tak M.
  • Winer Paul
  • Rao Valluri R.
  • Livengood Richard H.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 49  인용 특허 : 17

초록 ▼

A flip-chip having a decoupling capacitor electrically coupled to the backside thereof. The flip-chip includes a semiconductor substrate having first and second opposing surfaces with circuit elements formed within the first surface. A plurality of raised bump contacts are located on the first surfa

대표청구항

[ We claim:] [1.]1. An integrated circuit device comprising:a semiconductor substrate;a plurality of electrical interconnects coupled to said circuit elements; anda first decoupling capacitor disposed on a backside of said semiconductor substrate.

이 특허에 인용된 특허 (17) 인용/피인용 타임라인 분석

  1. Tokuda Masahide,JPX ; Kato Takeshi,JPX ; Itoh Hiroyuki,JPX ; Yagyu Masayoshi,JPX ; Fujita Yuuji,JPX ; Usami Mitsuo,JPX, Chip connection structure having diret through-hole connections through adhesive film and wiring substrate.
    상세보기
  2. Doyle Thomas R. (Leominster MA), Departiculation.
    상세보기
  3. McMahon John F., Flip-chip having electrical contact pads on the backside of the chip.
    상세보기
  4. Bhattacharyya Bidyut K. (Phoenix AZ) Tanahashi Shigeo (Kagoshima JPX), High performance and high capacitance package with improved thermal dissipation.
    상세보기
  5. Jacobs Scott L. (Chester VA) Nihal Perwaiz (Hopewell Junction NY) Ozmat Burhan (Peekskill NY) Schnurmann Henri D. (Monsey NY), High performance integrated circuit packaging structure.
    상세보기
  6. Bertin Claude Louis ; Ference Thomas George ; Howell Wayne John ; Sprogis Edmund Juris, Highly integrated chip-on-chip packaging.
    상세보기
  7. Bertin Claude Louis ; Howell Wayne John ; Tonti William Robert Patrick ; Zalesnski Jerzy Maria, Integrated high-performance decoupling capacitor.
    상세보기
  8. Bertin Claude Louis (South Burlington VT) Howell Wayne John (South Burlington VT) Hedberg Erik Leigh (Essex Junction VT) Kalter Howard Leo (Colchester VT) Kelley ; Jr. Gordon Arthur (Essex Junction V, Integrated mulitchip memory module, structure and fabrication.
    상세보기
  9. Greco Nancy Anne ; Harame David Louis ; Hueckel Gary Robert ; Kocis Joseph Thomas ; Ngoc Dominique Nguyen ; Stein Kenneth Jay, Metal-insulator-metal capacitor.
    상세보기
  10. Gardner Donald S., Method of forming a decoupling capacitor.
    상세보기
  11. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of planarizing tips of probe elements of a probe card assembly.
    상세보기
  12. Macdonald Perry A. (Culver City CA) Larson Lawrence E. (Bethesda MD) Case Michael G. (Thousand Oaks CA) Matloubian Mehran (Encino CA) Chen Mary Y. (Agoura CA) Rensch David B. (Thousand Oaks CA), Monolithic microwave integrated circuit and method.
    상세보기
  13. Lin Paul T. (Austin TX) McShane Michael B. (Austin TX), Overmolded semiconductor device having solder ball and edge lead connective structure.
    상세보기
  14. Thurairajaratnam Aritharan ; Cheng Wheling ; Kirkman Scott L., Semiconductor package having capacitive extension spokes and method for making the same.
    상세보기
  15. Leas James M. (South Burlington VT) Koss Robert W. (Burlington VT) Walker George F. (New York NY) Perry Charles H. (Poughkeepsie NY) Van Horn Jody J. (Underhill VT), Semiconductor wafer test and burn-in.
    상세보기
  16. Dozier ; II Thomas H. ; Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Sockets for electronic components and methods of connecting to electronic components.
    상세보기
  17. Pedder David John,GBX, Structure for testing bare integrated circuit devices.
    상세보기

이 특허를 인용한 특허 (49) 인용/피인용 타임라인 분석

  1. Bobba, Sudhakar; Thorp, Tyler; Trivedi, Pradeep, 180 degree bump placement layout for an integrated circuit power grid.
    상세보기
  2. Cloud, Eugene H.; Farrar, Paul A., Assemblies and packages including die-to-die connections.
    상세보기
  3. Harvey, Paul Marlan, Ball grid array package construction with raised solder ball pads.
    상세보기
  4. Harvey,Paul Marlan, Ball grid array package construction with raised solder ball pads.
    상세보기
  5. Ogawa, Kouki; Kodera, Eiji, Capacitor-built-in type printed wiring substrate, printed wiring substrate, and capacitor.
    상세보기
  6. Ogawa,Kouki; Kodera,Eiji, Capacitor-built-in type printed wiring substrate, printed wiring substrate, and capacitor.
    상세보기
  7. Siniaguine, Oleg, Clock distribution networks and conductive lines in semiconductor integrated circuits.
    상세보기
  8. Siniaguine,Oleg, Clock distribution networks and conductive lines in semiconductor integrated circuits.
    상세보기
  9. Copeland, Bruce A.; Gorrell, Rebecca Yung; Scheider, Donald W.; Takacs, Mark A.; Travis, Jr., Kenneth J.; Ulanmo, Peter O.; Wang, Jun, Corrosion-resistant electrode structure for integrated circuit decoupling capacitors.
    상세보기
  10. Sivasubramaniam, Suresh, Decoupling capacitor circuit assembly.
    상세보기
  11. Schaper, Leonard W., Decoupling capacitor for integrated circuit package and electrical components using the decoupling capacitor and associated methods.
    상세보기
  12. Akram, Salman, Die stacking scheme.
    상세보기
  13. Akram, Salman, Die stacking scheme.
    상세보기
  14. Akram,Salman, Die stacking scheme.
    상세보기
  15. Akram,Salman, Die stacking scheme.
    상세보기
  16. Akram,Salman, Die stacking scheme.
    상세보기
  17. Cloud, Eugene H.; Farrar, Paul A., Die to die connection method and assemblies and packages including dice so connected.
    상세보기
  18. Cloud,Eugene H.; Farrar,Paul A., Die to die connection method and assemblies and packages including dice so connected.
    상세보기
  19. Yatsu,Hiroyuki; Suzuki,Nobuyuki, Electronic circuit unit and method of fabricating the same.
    상세보기
  20. Akashi, Tomoko, Flip chip ball grid array package.
    상세보기
  21. Towle, Steven; Tang, John; Vandentop, Gilroy, High performance, low cost microelectronic circuit package with interposer.
    상세보기
  22. Chen, Shih-Hung; Hsieh, Kuang-Yeu, Integrated circuit capacitor and method.
    상세보기
  23. Towle,Steven; Tang,John; Cuendet,John S.; Braunisch,Henning; Dory,Thomas S., Low cost microelectronic circuit package.
    상세보기
  24. Shah,Jitesh, Method and apparatus with power and ground strips for connecting to decoupling capacitors.
    상세보기
  25. Komatsu,Ryuji, Method for forming component mounting hole in semiconductor substrate.
    상세보기
  26. Towle,Steven; Jones,Martha; Vu,Quat T., Method for packaging a microelectronic device using on-die bond pad expansion.
    상세보기
  27. Harvey, Paul Marlan, Method of ball grid array package construction with raised solder ball pads.
    상세보기
  28. Pearson,Tom E.; Amir,Dudi I.; Dishongh,Terrance J., Method of creating solder bar connections on electronic packages.
    상세보기
  29. Vu, Quat T.; Ton, Tuy T.; Towle, Steven, Microelectronic device having signal distribution functionality on an interfacial layer thereof.
    상세보기
  30. Breisch, James E.; Beiley, Mark A., Multi-frequency power delivery system.
    상세보기
  31. Vieweg, Raymond A.; Wood, Dustin P.; Holmberg, Nicholas L., Multilayer capacitor with multiple plates per layer.
    상세보기
  32. Liu, Tao; Schiveley, Steve; Chu, Peir; Greenwood, Mike; Steyskal, Aaron J., Multiple electrode capacitor.
    상세보기
  33. Yang, Chih An, Noise eliminating system on chip and method of making same.
    상세보기
  34. Liou, Shiann-Ming; Sutardja, Sehat; Wu, Albert; Cheng, Chuan-Cheng; Wei, Chien-Chuan, Package assembly having a semiconductor substrate.
    상세보기
  35. Wu, Albert; Chen, Roawen; Han, Chung Chyung (Justin); Liou, Shiann-Ming; Wei, Chien-Chuan; Chang, Runzi; Wu, Scott; Cheng, Chuan-Cheng, Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate.
    상세보기
  36. Wu, Albert; Chen, Roawen; Han, Chung Chyung; Liou, Shiann-Ming; Wei, Chien-Chuan; Chang, Runzi; Wu, Scott; Cheng, Chuan-Cheng, Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate.
    상세보기
  37. Fukada,Masakazu; Nakajima,Dai; Takanashi,Ken, Power module.
    상세보기
  38. Masakazu Fukada JP; Dai Nakajima JP; Ken Takanashi JP, Power module.
    상세보기
  39. Seshan, Krishna, Selectable decoupling capacitors for integrated circuit and methods of use.
    상세보기
  40. Seshan, Krishna, Selectable decoupling capacitors for integrated circuit and methods of use.
    상세보기
  41. Seshan,Krishna, Selectable decoupling capacitors for integrated circuits and associated methods.
    상세보기
  42. Kang,Sun Won, Semiconductor chip package having decoupling capacitor and manufacturing method thereof.
    상세보기
  43. Ino, Yoshihiko, Semiconductor device and manufacturing method thereof.
    상세보기
  44. Lee, Byoung Hwa; Park, Min Cheol; Kwak, Ho Cheol; Ke, Haixin; Hubing, Todd Harvey, Semiconductor integrated circuit chip, multilayer chip capacitor and semiconductor integrated circuit chip package.
    상세보기
  45. Shiro Yoshida JP, Semiconductor integrated circuit having an improved grounding structure.
    상세보기
  46. Liu,Sheng Tsung, Semiconductor package.
    상세보기
  47. Vaiyapuri, Venkateshwaran, Semiconductor/printed circuit board assembly, and computer system.
    상세보기
  48. Searls,Damion T.; Roth,Weston C.; Jackson,James Daniel, Surface mount solder method and apparatus for decoupling capacitance and process of making.
    상세보기
  49. Rouse,Richard P., Wafer bonded MOS decoupling capacitor.
    상세보기

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