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Integrated circuit with borderless contacts 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/302
출원번호 US-0328190 (1999-06-08)
발명자 / 주소
  • Arafa Mohamed
  • Thompson Scott
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Seeley
인용정보 피인용 횟수 : 14  인용 특허 : 25

초록

An integrated circuit comprising a conductive region formed on a semiconductor substrate, a silicate glass layer formed on the conductive region, and an etch stop layer formed on the silicate glass layer. The integrated circuit also includes a borderless contact that is coupled to the conductive reg

대표청구항

[ What is claimed is:] [1.]1. A method for forming an integrated circuit comprising:forming a conductive region on a semiconductor substrate;forming a silicate glass layer on the conductive region;forming an etch stop layer on the silicate glass layer; andforming a borderless contact coupled to the

이 특허에 인용된 특허 (25)

  1. Joshi Rajiv V. (Yorktown Heights NY), Graded oxide/nitride via structure and method of fabrication therefor.
  2. Brigham Lawrence N. (Beaverton OR) Lee Yung-Huei (Sunnyvale CA) Chau Robert S. (Beaverton OR) Cotner Raymond E. (Beaverton OR), High tensile nitride layer.
  3. Richman Paul (St. James NY), Last-stage programming of semiconductor integrated circuits including selective removal of passivation layer.
  4. Moslehi Mehrdad M. (Dallas TX), Low-RC multi-level interconnect technology for high-performance integrated circuits.
  5. Ogawa Hisashi (Katano JPX) Naito Yasushi (Toyonaka JPX) Fukumoto Masanori (Osaka JPX), Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact windo.
  6. Madokoro Shoji (Tokyo JPX), Method for forming an electrode layer by a laser flow technique.
  7. Kobayashi Masato (Tokyo JPX) Yamaguchi Yoichi (Tokyo JPX), Method for forming silicon nitride film.
  8. Barber Jeffrey R. (Pittsburgh PA) Breiten Charles P. (Manassass VA) Stanasolovich David (Manassas VA) Theisen Jacob F. (Manassas VA), Method for making borderless contacts.
  9. Thakur Randhir P. S. (Boise ID), Method for optimizing thermal budgets in fabricating semconductors.
  10. Thakur Randir P. S. (Boise ID) Gonzalez Fernando (Boise ID), Method for optimizing thermal budgets in fabricating semiconductors.
  11. Maniar Papu D. (Austin TX) Fiordalice Robert W. (Austin TX), Method for providing trench isolation and borderless contact.
  12. Wu Der-Yuan,TWX, Method of forming self-aligned silicide in integrated circuit without causing bridging effects.
  13. Bryant Frank R. (Denton TX) Waters John L. (Carrollton TX), Method of forming tunneling diffusion barrier for local interconnect and polysilicon high impedance device.
  14. Gargini Paolo (Palo Alto CA) Beinglass Israel (Santa Clara CA) Ahlquist Norman (Menlo Park CA), Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate.
  15. Yau Leopoldo D. (Portland OR) Chen Shih-ou (Fremont CA) Lin Yih S. (Beaverton OR), Method of making a silicon nitride resistor using plasma enhanced chemical vapor deposition.
  16. Haluska Loren A. (Midland MI) Michael Keith W. (Midland MI) Tarhay Leo (Sanford MI), Multilayer ceramics from silicate esters.
  17. Yokoi Katsuyuki (Shizuoka JPX) Suga Shigeru (Shizuoka JPX) Fujioka Toshio (Shizuoka JPX), Plasma vapor deposition of an improved passivation film using electron cyclotron resonance.
  18. Yoo Chue-San (Hsin-Chuang ; Taipei TWX), Polycide gate MOSFET process for integrated circuits.
  19. Givens John H. (Essex VT) Nakos James S. (Essex VT) Burke Peter A. (Milton VT) Hill Craig M. (Essex Junction VT) Lam Chung H. (Williston VT), Process for improving sheet resistance of an integrated circuit device gate.
  20. Raby Joseph S. (W. Melbourne FL), Process using tungsten for multilevel metallization.
  21. Balasubramanyam Karanam ; Gall Martin ; Gambino Jeffrey P. ; Mandelman Jack A., Reduction of gate-induced drain leakage in semiconductor devices.
  22. Wei Che-Chia (Plano TX) Tang Thomas E. (Dallas TX) Bohlman James G. (Forney TX) Douglas Monte A. (Coppell TX), Selective silicidation process using a titanium nitride protective layer.
  23. Kyuragi, Hakaru; Oikawa, Hideo, Semiconductor device and process for manufacturing the same.
  24. Watanabe Tohru (Yokohama JPX) Okumura Katsuya (Yokohama JPX), Semiconductor substrate surface processing method using combustion flame.
  25. Chen Fusen (Dallas TX) Bryant Frank R. (Denton TX) Dixit Girish (Dallas TX), Structure and method for contacts in CMOS devices.

이 특허를 인용한 특허 (14)

  1. Ye, Qiuyi; Tonti, William R.; Li, Yujun, Dual work function semiconductor structure with borderless contact and method of fabricating the same.
  2. Ye, Qiuyi; Tonti, William R.; Li, Yujun, Dual work function semiconductor structure with borderless contact and method of fabricating the same.
  3. Ye,Qiuyi; Tonti,William R.; Li,Yujun, Dual work function semiconductor structure with borderless contact and method of fabricating the same.
  4. Yong, Chih Ping; Chew, Peter; Yeap, Chuin Boon; Yap, Hoon Lian; Singh, Ranbir; Rossi, Nace; Lim, Jovin, Integrated circuit system with contact distribution film.
  5. Arafa, Mohamed; Thompson, Scott, Integrated circuit with borderless contacts.
  6. Hoffmann,Thomas; Auth,Chris; Armstrong,Mark; Cea,Stephen, Integrated circuit with improved channel stress properties and a method for making it.
  7. Zhu, Huilong; Zhong, Huicai; Leobandung, Effendi, Method and structure for forming self-aligned, dual stress liner for CMOS devices.
  8. Zhu,Huilong; Zhong,Huicai; Leobandung,Effendi, Method and structure for forming self-aligned, dual stress liner for CMOS devices.
  9. Yoon, Jun Ho, Method for forming a borderless contact of a semiconductor device.
  10. Dyer,Thomas W.; Yang,Haining, Method for forming self-aligned, dual silicon nitride liner for CMOS devices.
  11. Alex See SG; Kok Hin Teo SG; Kok Hiang Tang SG, Methods for eliminating metal corrosion by FSG.
  12. Gu,Shioun; Allman,Derryl J.; McGrath,Peter, Semiconductor chip with borderless contact that avoids well leakage.
  13. Zhu,Huilong; Tessier,Brian L.; Zhong,Huicai; Li,Ying, Undercut and residual spacer prevention for dual stressed layers.
  14. Weimer, Ronald A.; Ping, Er-Xuan, Use of atomic oxygen process for improved barrier layer.
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