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Method and apparatus for burn-in and test of field emission displays 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/00
출원번호 US-0258265 (1999-02-26)
발명자 / 주소
  • Browning Jim
  • Xia Zhongyi
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Nixon & Vanderhye P.C.
인용정보 피인용 횟수 : 12  인용 특허 : 17

초록

A method and apparatus which provides for continual monitoring of the electrical and optical performance of one or more field emission display devices while the devices are burned-in is for the purpose of proper aging and testing of screen phosphors and semiconductor circuitry as well as determining

대표청구항

[ What is claimed is:] [1.]1. A method of burning-in and testing of field emission display devices comprising:loading at least one of the devices into an oven and operating the oven at an oven temperature in the range from approximately 20.degree. C. to approximately 125.degree. C.;applying an opera

이 특허에 인용된 특허 (17)

  1. Eliashberg Victor M. ; Prakash Kombupalayam M., Apparatus for testing an integrated circuit in an oven during burn-in.
  2. Xia Zhong-Yi ; Kreipl Dwayne ; Piper Glenn, Current monitor for field emission displays.
  3. Casper Stephen L. (Boise ID) Lowrey Tyler A. (Boise ID), Flat panel display in which low-voltage row and column address signals control a much pixel activation voltage.
  4. Tuttle Mark E. (Boise ID) Doan Trung T. (Boise ID) Fox Angus C. (Boise ID) Sandhu Gurtej S. (Boise ID) Stroupe Hugh E. (Boise ID), Method and apparatus for improving planarity of chemical-mechanical planarization operations.
  5. Dennison Charles H. (Boise ID), Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer.
  6. Cathey David A. (Boise ID) Tjaden Kevin (Boise ID), Method for forming a substantially uniform array of sharp tips.
  7. Reinberg Alan R. (Westport CT) Rhodes Howard E. (Boise ID), Method of creating sharp points and other features on the surface of a semiconductor substrate.
  8. Lowrey Tyler A. (Boise ID) Doan Trung T. (Boise ID) Cathey David A. (Boise ID) Rolfson J. Brett (Boise ID), Method to form high aspect ratio supports (spacers) for field emission display using micro-saw technology.
  9. Doan Trung T. (Boise ID) Lowrey Tyler A. (Boise ID) Cathey David A. (Boise ID) Rolfson J. Brett (Boise ID), Method to form self-aligned gate structures and focus rings.
  10. Doan Trung T. (Boise ID) Rolfson J. Brett (Boise ID) Lowrey Tyler A. (Boise ID) Cathey David A. (Boise ID), Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technol.
  11. Sandhu Gurtej S. (Boise ID), Method to form self-aligned tips for flat panel displays.
  12. Farnworth Warren M. (Boise ID), Micro-pillar fabrication utilizing a stereolithographic printing process.
  13. Sharpes Michael J. ; Totorica Robert L., Modular design for an IC testing burn-in oven.
  14. Cathey David A. (Boise IA) Yu Chris C. (Boise IA) Doan Trung T. (Boise IA) Lowrey Tyler A. (Boise IA) Rolfson J. Brett (Boise IA), Spacers for field emission display fabricated via self-aligned high energy ablation.
  15. Cathey David A. (Boise ID) Hofmann James J. (Boise ID) Dynka Danny (Boise ID) Stansbury Darryl M. (Boise ID), Spacers for large area displays.
  16. Heo Kyeong Il,KRX ; Kim Tae Lyun,KRX, Test system for variable selection of IC devices for testing.
  17. Orihashi Ritsuro (Yokohama JPX) Kendo Kosuke (Yokohama JPX) Hayashi Yoshihiko (Yokosuka JPX), .

이 특허를 인용한 특허 (12)

  1. Floyd, John; Dar, Iqbal; Obradovic, Mila; Humberson, Jerome, Automated monitoring system, virtual oven and method for stress testing logically grouped modules.
  2. Jaworski,Douglas S.; Snider,Daniel W., Boundary-scan system architecture for remote environmental testing.
  3. Conti,Dennis R.; Gamache,Roger; Gardell,David L.; Knox,Marc D.; Van Horn,Jody J, Device burn in utilizing voltage control.
  4. Jiang, Yan; Tang, Xianzhen; Lu, Xiaoming; Li, Dan; Gong, Xiaowei; Kim, Chiyoung, High temperature and high humidity testing device and high temperature and high humidity testing system.
  5. Hsu,Yu Yun, Light-on aging test system for flat panel display.
  6. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Method and apparatus for no lead semiconductor package.
  7. Nuanwan, Suweat; Tayaphat, Prayoch; Itdhiamornkulchai, Apichai, Method and apparatus to prevent double semiconductor units in test socket.
  8. Yong Jaimsomporn TH; Tanawat Boutngam TH; Narupon Tabtimted TH, Method and system for adapting burn-in boards to multiple burn-in systems.
  9. Jaworski,Douglas S.; Snider,Daniel W., Method and system for backplane testing using generic boundary-scan units.
  10. Albert, Jason T.; Bronk, William T.; Eby, Timothy J.; Hamilton, Michael J.; James, Norman K., Method of and system for functionally testing multiple devices in parallel in a burn-in-environment.
  11. Sangaunwong, Saruch; Tayaphat, Prayoch; Boonareeroj, Pinut, Strip socket for testing and burn-in having recessed portions with material that extends across a bottom surface of the corresponding semiconductor device.
  12. Sangaunwong, Saruch; Tayaphat, Prayoch; Boonareeroj, Pinut, Strip socket having a recessed portions in the base to accept bottom surface of packaged semiconductor devices mounted on a leadframe for testing and burn-in.
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