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Method and system for arbitrating path contention in a crossbar interconnect network 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0994527 (1997-12-19)
발명자 / 주소
  • Van Krevelen Christopher J.
  • Nelson Reed S.
  • Hodapp
  • Jr. Don J.
  • Hamre John D.
출원인 / 주소
  • Storage Technology Corporation
대리인 / 주소
    Brooks & Kushman P.C.
인용정보 피인용 횟수 : 42  인용 특허 : 22

초록

A method and system for transmitting data among a plurality of cards in a crossbar interconnect network having a plurality of cards each having source paths and destination paths utilizes a plurality of source arbitrators and a plurality of destination arbitrators each associated with the cards. The

대표청구항

[ What is claimed is:] [24.]24. A scaleable apparatus for transmitting data among a plurality of cards in a crossbar interconnect network, each of the plurality of cards having source paths for originating the data and destination paths for receiving the data, the apparatus comprising:each of the ca

이 특허에 인용된 특허 (22)

  1. Sakai Tomohiro (Tokyo JPX), Connection apparatus for magnetic disk device.
  2. Kim Sun-gi,KRX, DMA system for re-arbitrating memory access priority during DMA transmission when an additional request is received.
  3. Frankeny Richard Francis ; Venkatramani Krisnamurthy, Data processing system and method for implementing a switch protocol in a communication system.
  4. Okabayashi Ichiro,JPX ; Kaneko Katsuyuki,JPX ; Kadota Hiroshi,JPX, Data transfer apparatus and system providing high speed switching to allow for high speed data transfer between one devi.
  5. Lee Hyeun Tae,KRX ; Lee Keun Woo,KRX, Data transmitting/receiving method using distributed path control in data switching system.
  6. Farmer Michael Edward (Eagan MN) Murphy Steven Allen (Apple Valley MN) Stevens Rick Clevie (Apple Valley MN), Deadlock avoidance for switched interconnect bus systems.
  7. Chang Robert W. (Oakton VA), Distributed programmable priority arbitration.
  8. Osaki Yoshiro (Tokyo JPX), Exchange control system using a multiprocessor for setting a line in response to line setting data.
  9. Kent Allan R. (Arlington MA) Goodstein Ronald E. (Newton MA) Henry Barry A. (Penacook NH), Hierarchical arbitration system.
  10. Gavin Derwin DeLon ; Gillen Daniel Cletus ; Haug Jessie Ann Hays ; Partridge James Britt ; Russell Lance Warren ; Smith Eldon Perry, High performance communications path.
  11. Atac Robert (Aurora IL) Fischler Mark S. (Warrenville IL) Husby Donald E. (DeKalb IL), Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system.
  12. Stephenson Bricky A. (Chippewa Falls WI) Logghe Peter G. (Chippewa Falls WI), Memory interconnect network having separate routing networks for inputs and outputs using switches with FIFO queues and.
  13. Simcoe Robert ; Thomas Robert E. ; Varghese George, Method and apparatus for dynamically controlling data routes through a network.
  14. Van Loo William C., Method and apparatus for fast-forwarding slave request in a packet-switched computer system.
  15. Bell D. Michael ; Gonzales Mark A. ; Meredith Susan S., Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge.
  16. Benton Michael K. (Malvern PA) Gold Anthony P. (Wayne PA) Schranz Richard A. (Norristown PA), Method and apparatus for simultaneous interconnection of multiple requestors to multiple memories.
  17. Chou Ger-Chih (San Jose CA) Dahlgren Kent Blair (San Jose CA) Hsieh Wen-Jai (Palo Alto CA), Network switch with arbitration sytem.
  18. Brewer Tony Mahlon ; Watson Thomas Lee ; Chastain David Michael, Parallel processing computer system having shared coherent memory and interconnections utilizing separate undirectional.
  19. Brewer Tony M. (Dallas TX) Watson Thomas L. (Dallas TX) Chastain David M. (Plano TX), Parallel processing computer system interconnections utilizing unidirectional communication links with separate request.
  20. Stevens Rick (Apple Valley MN), Self-routing multi-stage photonic interconnect.
  21. Foster Eric M. ; Franklin Dennis E. ; Jackowski Stefan P. ; Wallach David, Shared access control device for integrated system with multiple functional units accessing external structures over multiple data buses.
  22. Crowther William R. ; Brandt William P., Technique for connecting cards of a distributed network switch.

이 특허를 인용한 특허 (42)

  1. Singh, Rajesh, Arbitration circuit with plural arbitration processors using memory bank history.
  2. Walton, John K.; Castel, Daniel; Chilton, Kendell Alan, Data storage system.
  3. Walton,John K.; Castel,Daniel; Chilton,Kendell Alan, Data storage system.
  4. Zani, Mark; Romano, Scott; Dellicicchi, Alfred, Data storage system having master-slave arbiters.
  5. Wilson,Paul C.; Zani,Mark; Khan,Farouk; MacLellan,Christopher S.; Walton,John K.; MacArthur,Steven; Chilton,Kendall A.; Tuccio,William; Thibault,Robert A., Data storage system having point-to-point configuration.
  6. Ofek,Yuval; Black,David L.; Macarthur,Stephen D.; Wheeler,Richard; Thibault,Robert, Data storage system having separate data transfer section and message network.
  7. MacArthur,Stephen D.; Black,David; Wheeler,Richard, Data storage system having separate data transfer section and message network having bus arbitration.
  8. Thibault, Robert, Data storage system having separate data transfer section and message network with bus arbitration.
  9. MacArthur,Stephen D., Data storage system having separate data transfer section and message network with plural directions on a common printed circuit board.
  10. Black,David L.; Wheeler,Richard; Thibault,Robert; MacArthur,Stephen D.; Ofek,Yuval, Data storage system having separate data transfer section and message network with plural directors on a common printed circuit board and redundant switching networks.
  11. Kallat, Avinash; Thibault, Robert; MacArthur, Stephen D., Data storage system having separate data transfer section and message network with status register.
  12. Nishiyashiki, Masaru, Data transfer circuit and data transfer method.
  13. Masayuki Furuta JP; Kouki Shigaki JP; Chikara Shibagaki JP, Data transfer making efficient use of time concerning bus arbitration.
  14. Kallat, Avinash; Thibault, Robert, Direct memory access (DMA) transmitter.
  15. Watanabe, Kenichi, Electronic apparatus and signal disconnection/connection method.
  16. Chow, David Q.; Lee, Charles C.; Yu, Frank I-Kang; Ma, Abraham C.; Shen, Ming-Shiang, Extended SD and microSD hosts and devices with USB-like high performance packetized interface and protocol.
  17. D'Errico, Matthew J., Method and apparatus for balancing workloads among paths in a multi-path computer system based on the state of previous I/O operations.
  18. Matthew J. D'Errico, Method and apparatus for balancing workloads among paths in a multi-path computer system based on the state of previous I/O operations.
  19. Moran, Christine E.; Akers, Matthew D.; Pagan, Annette, Method and system for controlling transmission and execution of commands in an integrated circuit device.
  20. Black,David L.; MacArthur,Stephen D.; Wheeler,Richard G.; Thibault,Robert A.; Shulman,Michael, Method for message transfer in computer storage system.
  21. Yochai, Yechiel; Raizen, Helen; Sandstrom, Harold M.; Epstein, Edith, Methods and systems for dynamic division of path capacity.
  22. Donald Robert Pannell ; Robert D. Hemming, Modular network switch with peer-to-peer address mapping communication.
  23. Kashiwagi, Shinji; Nakajima, Hiroyuki, Multiplexing commands from processors to tightly coupled coprocessor upon state based arbitration for coprocessor resources.
  24. Pannell, Donald Robert, Network switch with head of line input buffer queue clearing.
  25. Pannell, Donald Robert, Network switch with zero latency flow control.
  26. Wang, Feng; Nowak, Matthew Michael; Kim, Jonghae, Partitioning a crossbar interconnect in a multi-channel memory system.
  27. Jacobs, Mick R.; Benning, Michael A., Prioritization and preemption of data frames over a switching fabric.
  28. Jacobs, Mick R.; Benning, Michael A., Prioritization and preemption of data frames over a switching fabric.
  29. Jacobs,Mick R.; Benning,Michael A., Prioritization and preemption of data frames over a switching fabric.
  30. Torza, Anthony, Reconfigurable switch having an overlapping Clos Architecture.
  31. Raizen, Helen S.; Camp, Jeffrey; Bappe, Michael E., Selective I/O to logical unit when encrypted, but key is not available or when encryption status is unknown.
  32. Shamarao, Prashant; Lukanc, Jeffrey, Signal conditioner for high-speed data communications.
  33. Milbredt, Paul, Star coupler for a bus system, bus system having such a star coupler and method for interchanging signals in a bus system.
  34. Mizobata,Norihiko, Stream processor.
  35. Lin, Ching-Chung, Switch apparatus and electronic device.
  36. Adam, Joel F.; Engelkemier, Darren; Klausmeier, Daniel E., Switch fabric architecture and techniques for implementing rapid hitless switchover.
  37. Adam,Joel F.; Engelkemier,Darren; Klausmeier,Daniel E., Switch fabric architecture and techniques for implementing rapid hitless switchover.
  38. Sakaue, Kenji, Switching element and packet switch.
  39. Struhsaker, Paul F.; Denton, James S.; McGee, Gregory L., System and method for providing an improved common control bus for use in on-line insertion of line replaceable units in wireless and wireline access systems.
  40. Kamhine,Eli, System and method for scheduling a cross-bar.
  41. Raizen, Helen S.; Freund, David W.; Harwood, John; Bappe, Michael E., Systems and methods for accessing storage or network based replicas of encrypted volumes with no additional key management.
  42. Raizen, Helen S.; Harwood, John; Bappe, Michael E.; Kothandan, Sathiyamoorthy; Epstein, Edith, Systems and methods for selective encryption of operating system metadata for host-based encryption of data at rest on a logical unit.
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