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Metallization outside protective overcoat for improved capacitors and inductors 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/00
출원번호 US-0183821 (1998-10-30)
발명자 / 주소
  • Erdeljac John P.
  • Hutter Louis Nicholas
  • Khatibzadeh M. Ali
  • Arch John Kenneth
출원인 / 주소
  • Texas Instruments Incorporated
대리인 / 주소
    Brady, III
인용정보 피인용 횟수 : 87  인용 특허 : 13

초록

A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.

대표청구항

[ What is claimed is:] [1.]1. An integrated circuit device, comprising:a semiconductor substrate;a field oxide region formed over a first portion of said semiconductor substrate;a polysilicon layer formed over and insulated from a second portion of said semiconductor substrate;a first insulator laye

이 특허에 인용된 특허 (13)

  1. Lee Chwan-Ying,TWX ; Huang Tzuen-Hsi,TWX, Integrated circuit inductor structure formed employing copper containing conductor winding layer clad with nickel contai.
  2. Keil Richard F. (Jonesville VT) Kelkar Ram (South Burlington VT) Novof Ilya I. (Essex Junction VT) Oppold Jeffery H. (Richmond VT) Short Kenneth D. (Essex Junction VT) Wyatt Stephen D. (Jericho VT), Integrated compact capacitor-resistor/inductor configuration.
  3. Ramakrishnan E. S. ; Weisman Douglas H., Integrated inductor and capacitor on a substrate and method for fabricating same.
  4. Lee William W. Y., Method for fabricating air-insulated multilevel metal interconnections for integrated circuits.
  5. Jain Vivek (Milpitas CA) Pramanik Dipankar (Cupertino CA) Nariani Subhash (San Jose CA), Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors.
  6. Eklund Robert H. (Plano TX) Prinslow Douglas A. (Plano TX) Scott David B. (Plano TX), Method of forming a polysilicon resistor using an oxide, nitride stack.
  7. Pan Ju-Don T. (Austin TX), Method of making an electrical multilayer interconnect.
  8. Dow Stephen (Chandler AZ) Maass Eric C. (Scottsdale AZ) Marlin Bill (Phoenix AZ), Method of making an electronic device having an integrated inductor.
  9. De Bruin Leendert (Eindhoven NLX), Method of manufacturing a semiconductor device having conductive material provided in an insulating layer.
  10. Efland Taylor R. ; Cotton David ; Skelton Dale J., Multiple transistor integrated circuit with thick copper interconnect.
  11. Havemann Robert H. (Garland TX) Gnade Bruce E. (Dallas TX) Cho Chih-Chen (Richardson TX), Porous dielectric material with a passivation layer for electronics applications.
  12. Delgado Jose Avelino ; Gaul Stephen Joseph, Pre-bond cavity air bridge.
  13. Lin Yung-Fa,TWX, Process for creating vias using pillar technology.

이 특허를 인용한 특허 (87)

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