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High-Q inductive elements 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01F-005/00
출원번호 US-0460655 (1999-12-14)
발명자 / 주소
  • Farrar Paul A.
  • Forbes Leonard
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg, Woessner & Kluth, P.A.
인용정보 피인용 횟수 : 11  인용 특허 : 25

초록

A first insulator is formed on a base layer. A first conductor is formed on the first insulator. The first conductor is patterned. A second insulator is formed over the first insulator. A via hole is formed in the second insulator and is electrically coupled to the first conductor through the via ho

대표청구항

[ We claim:] [1.]1. An inductive element on a substrate, comprising:a base layer;a first insulator formed on the base layer;a first conductor formed on the first insulator;a second insulator formed on the first insulator;a second conductor, having first and second branches that are substantially par

이 특허에 인용된 특허 (25)

  1. Beyer Klaus D. (Poughkeepsie NY) Ku San-Mei (Poughkeepsie NY) Silvestri Victor J. (Hopewell Junction NY) Yapsir Andrie S. (Pleasant Valley NY), Buried air dielectric isolation of silicon islands.
  2. Gonzales Fernando (Boise ID), Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertic.
  3. Kim Jong S. (Sungnam KRX) Yoon Hee-Koo (Seoul KRX) Choi Chung G. (Kyoungki-Do KRX), Dynamic random access memory having a vertical transistor.
  4. Yamamoto Tadashi (Kawasaki JPX) Sawada Shizuo (Yokohama JPX), Dynamic random access memory having bit lines buried in semiconductor substrate.
  5. Lee Kyu-Woong (Arlington MA) Durschlag Mark S. (Natick MA) Day John (Lexington MA), Evaporated thick metal and airbridge interconnects and method of manufacture.
  6. Prasad Jayasimha S. (Tigard OR) Park Song W. (Aloha OR) Vetanen William A. (Sherwood OR) Beers Irene G. (Sherwood OR) Haynes Curtis M. (Portland OR), Implant-free heterojunction bioplar transistor integrated circuit process.
  7. Beyer Klaus D. (Poughkeepsie NY) Silvestri Victor J. (Hopewell Junction NY) Yapsir Andrie S. (Pleasant Valley NY), Isolated films using an air dielectric.
  8. Noble Wendell, Memory array having a digit line buried in an isolation region and method for forming same.
  9. Houston Theodore W. (Richardson TX), Method for forming a semiconductor on insulator device.
  10. Klatskin Jerome Barnard (Princeton Junction NJ) Rosen Arye (Cherry Hill NJ), Method of electrically interconnecting semiconductor elements.
  11. Tam Gordon (Chandler AZ) Granick Lisa R. (Philadelphia PA), Method of fabricating airbridge metal interconnects.
  12. Yang Ming-Tzong (Hsin-Chu TWX) Hong Gary (Hsin-Chu TWX), Method of fabrication of MOSFET device with buried bit line.
  13. Chen Fusen E. (Dallas TX) Liou Fu-Tai (Carrollton TX) Dixit Girish A. (Dallas TX), Method of forming vias.
  14. Grader Gideon S. (Haifa NJ ILX) Johnson ; Jr. David W. (Pluckemin NJ) Roy Apurba (Rockwall TX) Thomson ; Jr. John (Spring Lake NJ), Method of making a multilayer monolithic magnet component.
  15. Chino Toyoji (Osaka JPX) Matsuda Kenichi (Osaka JPX) Shibata Jun (Osaka JPX), Method of making semiconductor device with air-bridge interconnection.
  16. Cha Sung W. (Cambridge MA) Suh Nam P. (Sudbury MA) Baldwin Daniel F. (Medford MA) Park Chul B. (Cambridge MA), Microcellular thermoplastic foamed with supercritical fluid.
  17. Nakano Hirofumi (Itami JPX), Multi-layer wiring.
  18. Miura Takao,JPX ; Yamauchi Tunenori,JPX ; Monma Yoshinobu,JPX ; Goto Hiroshi,JPX, Process for manufacturing semiconductor devices separated by an air-bridge.
  19. Gardner Donald S., Process of fabricating embedded ground plane and shielding structures using sidewall insulators in high frequency circu.
  20. Klose Helmut,DEX ; Weber Werner,DEX ; Bertagnolli Emmerich,DEX ; Koppe Siegmar,DEX ; Hubner Holger,DEX, Semiconductor component for vertical integration and manufacturing method.
  21. Ohya Shuichi,JPX ; Sakao Masato,JPX ; Takaishi Yoshihiro,JPX ; Kajiyana Kiyonori,JPX ; Akimoto Takeshi,JPX ; Oguro Shizuo,JPX ; Shishiguchi Seiichi,JPX, Semiconductor memory device having trench isolation regions and bit lines formed thereover.
  22. Baldwin Daniel F. (Medford MA) Suh Nam P. (Sudbury MA) Park Chul B. (Cambridge MA) Cha Sung W. (Cambridge MA), Supermicrocellular foamed materials.
  23. Bertin Claude L. (South Burlington VT) Farrar ; Sr. Paul A. (South Burlington VT) Kalter Howard L. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT) van der Hoeven Willem B. (Jericho VT) Whi, Three dimensional multichip package methods of fabrication.
  24. Bertin Claude L. (South Burlington) Farrar ; Sr. Paul A. (South Burlington) Kalter Howard L. (Colchester) Kelley ; Jr. Gordon A. (Essex Junction) van der Hoeven Willem B. (Jericho) White Francis R. (, Three-dimensional multichip packages and methods of fabrication.
  25. Lu Chih-Yuan (Hsin-chu TWX), Vertical DRAM cross point memory cell and fabrication method.

이 특허를 인용한 특허 (11)

  1. Farrar, Paul A.; Noble, Wendell P., Buried conductors.
  2. Forbes, Leonard, CMOS voltage controlled phase shift oscillator.
  3. Paul A. Farrar ; Leonard Forbes, High-Q inductive elements.
  4. Forbes,Leonard, Method and apparatus for providing clock signals at different locations with minimal clock skew.
  5. Farrar, Paul A.; Noble, Wendell P., Method of forming buried conductors.
  6. Parks, Jay S., Microelectronic die including low RC under-layer interconnects.
  7. Parks, Jay S., Microelectronic die including low RC under-layer interconnects.
  8. Hopper, Peter J.; Johnson, Peter; Hwang, Kyuwoon; Lindorfer, Philipp, On-chip power inductor.
  9. Ahn, Kie Y.; Forbes, Leonard, Semiconductor device with electrically coupled spiral inductors.
  10. Ahn,Kie Y.; Forbes,Leonard, Semiconductor device with electrically coupled spiral inductors.
  11. Ahn,Kie Y; Forbes,Leonard, Semiconductor device with electrically coupled spiral inductors.
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