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Interconnect structure and method for forming the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/469
출원번호 US-0256211 (1999-02-24)
우선권정보 JP0044814 (1998-02-26)
발명자 / 주소
  • Aoi Nobuo,JPX
출원인 / 주소
  • Matsushita Electric Industrial Co., Ltd., JPX
대리인 / 주소
    Robinson
인용정보 피인용 횟수 : 40  인용 특허 : 5

초록

An interconnection structure includes an interlevel insulating film, made of organic-containing silicon dioxide, between lower- and upper-level metal interconnects. A phenyl group, bonded to a silicon atom, is introduced into silicon dioxide in the organic-containing silicon dioxide.

대표청구항

[ What is claimed is:] [1.]1. A method for forming an interconnection structure, comprising the steps of:forming an interlevel insulating film out of organic-containing silicon dioxide over lower-level metal interconnects by a CVD process using a reactive gas containing phenyltrimethoxy silane, a ph

이 특허에 인용된 특허 (5)

  1. Motoyama Takahiko (Tokyo JPX) Miyata Yoshio (Chigasaki JPX) Matsui Fumio (Yokohama JPX) Namba Yoichi (Yokohama JPX) Kamoi Noritoshi (Matsudo JPX) Ohwaki Yukari (Kawasaki JPX), Ladder silicone oligomer composition.
  2. Dean Robert Earl (High Bridge NJ) Foo Pang-Dow (Berkeley Heights NJ) Lory Earl Ryan (Pennington NJ) Olmer Leonard Jay (Hopewell NJ), Low temperature deposition of silicon oxides for device fabrication.
  3. Yau Wai-Fan ; Cheung David ; Jeng Shin-Puu ; Liu Kuowei ; Yu Yung-Cheng, Method of depositing a low k dielectric with organo silane.
  4. Inohara Masahiro,JPX ; Shibata Hideki,JPX ; Matsuno Tadashi,JPX, Method of making semiconductor apparatus having wiring groove and contact hole formed in a self-alignment manner.
  5. Avanzino Steven ; Gupta Subhash ; Klein Rich ; Luning Scott D. ; Lin Ming-Ren, Self aligned via dual damascene.

이 특허를 인용한 특허 (40)

  1. Li,Lihua; Huang,Tzu Fang; Sugiarto, legal representative,Jerry; Xia,Li Qun; Lee,Peter Wai Man; M'Saad,Hichem; Cui,Zhenjiang; Park,Sohyun; Sugiarto, deceased,Dian, Adhesion improvement for low k dielectrics.
  2. Li,Lihua; Huang,Tzu Fang; Sugiarto, legal representative,Jerry; Xia,Li Qun; Lee,Peter Wai Man; M'Saad,Hichem; Cui,Zhenjiang; Park,Sohyun; Sugiarto,Dian, Adhesion improvement for low k dielectrics.
  3. Rajagopalan,Nagarajan; Shek,Meiyee; Lee,Albert; Lakshmanan,Annamalai; Xia,Li Qun; Cui,Zhenjiang, Adhesion improvement for low k dielectrics to conductive materials.
  4. Lee,Albert; Lakshmanan,Annamalai; Kim,Bok Hoen; Xia,Li Qun; Shek Le,Mei Yee, Bi-layer approach for a hermetic low dielectric constant layer for barrier applications.
  5. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
  6. Farrar, Paul A., Damascene structure and method of making.
  7. Paul A. Farrar, Damascene structure and method of making.
  8. Farrar, Paul A., Damascene structure with low dielectric constant insulating layers.
  9. Usami, Tatsuya, Dual damascene circuit with upper wiring and interconnect line positioned in regions formed as two layers including organic polymer layer and low-permittivity layer.
  10. Lakshmanan,Annamalai; Lee,Albert; Lee,Ju Hyung; Kim,Bok Hoen, Hermetic low dielectric constant layer for barrier applications.
  11. Yim,Kang Sub; Tam,Melissa M.; Sugiarto,Dian; Lang,Chi I; Lee,Peter Wai Man; Xia,Li Qun, Low dielectric (low k) barrier films with oxygen doping by plasma-enhanced chemical vapor deposition (PECVD).
  12. Xia, Li-Qun; Xu, Ping; Yang, Louis; Huang, Tzu-Fang; Zhu, Wen H., Method for depositing a low k dielectric film (K>3.5) for hard mask application.
  13. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Method for fabricating circuitry component.
  14. Yuasa, Hiroshi, Method for fabricating metal interconnect in a carbon-containing silicon oxide film.
  15. Yuasa,Hiroshi, Method for forming metal interconnect in a carbon containing silicon oxide film.
  16. Leu, Jihperng; Wu, Chih-I; Zhou, Ying; Kloster, Grant M., Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics.
  17. Yim, Kang Sub; Tam, Melissa M.; Sugiarto, Dian; Lang, Chi-I; Lee, Peter Wai-Man; Xia, Li-Qun, Method for producing semiconductor including forming a layer containing at least silicon carbide and forming a second layer containing at least silicon oxygen carbide.
  18. Lee,Ju Hyung; Xu,Ping; Venkataraman,Shankar; Xia,Li Qun; Han,Fei; Yieh,Ellie; Nemani,Srinivas D.; Yim,Kangsub; Moghadam,Farhad K.; Sinha,Ashok K.; Zheng,Yi, Method of depositing dielectric materials including oxygen-doped silicon carbide in damascene applications.
  19. Xia,Li Qun; Xu,Ping; Yang,Louis, Method of depositing low K barrier layers.
  20. Xia, Li-Qun; Xu, Ping; Yang, Louis, Method of depositing low k barrier layers.
  21. Xia,Li Qun; Xu,Ping; Yang,Louis, Method of depositing low k barrier layers.
  22. Gaillard, Frederick; Xia, Li-Qun; Lim, Tian-Hoe; Yieh, Ellie, Method of depositing organosilicate layers.
  23. Naito, Hiroshi, Method of fabricating an integrated circuit having a multi-layer structure with a seal ring.
  24. Li,Lihua; Huang,Tzu Fang; Xia,Li Qun, Method of improving stability in low k barrier layers.
  25. Rantala, Juha T.; Paulasaari, Jyri; Kylmä, Janne, Organo-silsesquioxane polymers for forming low-k dielectrics.
  26. Kanamura,Ryuichi, Production method of semiconductor device.
  27. Nakamura, Shunji, Semiconductor device and its manufacture.
  28. Nakamura, Shunji, Semiconductor device with wiring embedded in trenches and vias.
  29. Yoon, Junho; Min, Gyungjin; Park, Jaehong; Jang, Yongmoon; Han, Je-Woo, Semiconductor devices including a support for an electrode and methods of forming semiconductor devices including a support for an electrode.
  30. Yoon, Junho; Min, Gyungjin; Park, Jaehong; Jang, Yongmoon; Han, Je-Woo, Semiconductor devices including a support for an electrode and methods of forming semiconductor devices including a support for an electrode.
  31. Nobuo Matsuki JP; Yuichi Naito JP; Yoshinori Morisada JP; Aya Matsunoshita JP, Silicone polymer insulation film on semiconductor substrate and method for forming the film.
  32. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  33. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  34. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  35. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  36. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  37. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  38. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  39. Camillo-Castillo, Renata; Khater, Marwan H., Trench isolation structures and methods for bipolar junction transistors.
  40. Zheng, Yi; Nemani, Srinivas D.; Xia, Li-Qun, Two-layer film for next generation damascene barrier application with good oxidation resistance.
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