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A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equa

A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.

대표청구항 ▼

[ What is claimed is:] [1.]1. A semiconductor integrated circuit device comprising:a clock signal generator for outputting clock signals;a plurality of flip-flops for receiving said clock signals from said clock signal generator through clock lines; anda plurality of stages of clock drivers furnishe

[ What is claimed is:] [1.]1. A semiconductor integrated circuit device comprising:a clock signal generator for outputting clock signals;a plurality of flip-flops for receiving said clock signals from said clock signal generator through clock lines; anda plurality of stages of clock drivers furnished on clock lines ranging from said clock signal generator to said flip-flops;wherein differences between a maximum and a minimum length of the clock lines between first stage clock drivers and second stage clock drivers are smaller than differences between a maximum and a minimum length of the clock lines between last stage clock drivers and said flip-flops.