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Process for low-k dielectric with dummy plugs 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/476.3
출원번호 US-0228125 (1999-01-11)
발명자 / 주소
  • Yu Chen-Hua,TWX
  • Jeng Shwangming,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 25  인용 특허 : 7

초록

Low dielectric inter-metal dielectric (IMD) layers made of hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ) spin-on-glass do not have good thermal conductivity as compared to regular oxides, in addition the adhesion of HSQ or MSQ is worse than that of oxide to oxide layers Methods are di

대표청구항

[ What is claimed is:] [1.]1. A method of providing dummy plugs on a semiconductor wafer, comprising the steps of:depositing at least one set of an inter-metal dielectric layer and following metallization layer on top of said semiconductor wafer;providing each said metallization layer with a plurali

이 특허에 인용된 특허 (7)

  1. Cote Donna Rizzone ; Nguyen Son Van, Flowable spin-on insulator.
  2. Sakashita Kazuhiro (Hyogo JPX) Kato Shuichi (Hyogo JPX) Takimoto Isao (Hyogo JPX), Integrated circuit device having a geometry to enhance fabrication and testing and manufacturing method thereof.
  3. Kennell Mark E. ; Grubb Robert G. ; Seifarth Randy V. ; Steele Robert D., Method of assembling a turbine runner situated in a water passageway.
  4. Katto Hisao (Tokyo JPX) Sugiura June (Musashino JPX) Horino Nozomi (Higashiyamato JPX) Endo Akira (Hachiouji JPX) Takeuchi Yoshiharu (Koganei JPX) Arakawa Yuji (Kokubunji JPX), Method of making a semiconductor memory device.
  5. Wada Jun-ichi (Yokohama JPX) Kaneko Hisashi (Fujisawa JPX) Hayasaka Nobuo (Yokosuka JPX), Method of manufacture of semiconductor device.
  6. Sawada Hideki (Kyoto JPX) Ogata Hiromi (Kyoto JPX), Semiconductor chip having dummy pattern.
  7. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

이 특허를 인용한 특허 (25)

  1. Huang,Tai Chun; Lee,Tze Liang, Bonding pad and via structure design.
  2. Abraham, David W.; Keefe, George A.; Lavoie, Christian; Rothwell, Mary E., Chip mode isolation and cross-talk reduction through buried metal layers and through-vias.
  3. Abraham, David W.; Keefe, George A.; Lavoie, Christian; Rothwell, Mary E., Chip mode isolation and cross-talk reduction through buried metal layers and through-vias.
  4. Pangrle, Suzette K.; Okada, Lynne A.; Wang, Fei, Dual damascene metal interconnect structure with dielectric studs.
  5. Landis, Howard S., Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics.
  6. Landis,Howard S., Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics.
  7. Landis,Howard S., Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics.
  8. Chuang, Harry, Localized slots for stress relieve in copper.
  9. Chuang,Harry, Localized slots for stress relieve in copper.
  10. Chuang,Harry, Localized slots for stress relieve in copper.
  11. Woon-Yong Park KR; Bum-Ki Baek KR, Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films.
  12. Abraham, David W.; Chow, Jerry M.; Corcoles Gonzalez, Antonio D.; Keefe, George A.; Rothwell, Mary E.; Rozen, James R.; Steffen, Matthias, Method of fabricating a coplanar waveguide device including removal of spurious microwave modes via flip-chip crossover.
  13. Song, Jun-Ho; Park, Woon-Yong, Method of forming a thin film transistor array panel using photolithography techniques.
  14. Goebel, Thomas; Kaltalioglu, Erdem; Kim, Sun-Oo, Method of forming support structures for semiconductor devices.
  15. Lee, Tze-Liang; Huan, Yun-San, Pad structure to prompt excellent bondability for low-k intermetal dielectric layers.
  16. Lee, Tze-Liang; Huan, Yun-San, Pad structure to prompt excellent bondability for low-k intermetal dielectric layers.
  17. Mu, Zheng-Chang; Lin, Cheng-Wei; Liu, Kuang-Wen, Photo pattern method to increase via etching rate.
  18. Abraham, David W.; Chow, Jerry M.; Corcoles Gonzalez, Antonio D.; Keefe, George A.; Rothwell, Mary E.; Rozen, James R.; Steffen, Matthias, Removal of spurious microwave modes via flip-chip crossover.
  19. Abraham, David W.; Chow, Jerry M.; Corcoles Gonzalez, Antonio D.; Keefe, George A.; Rothwell, Mary E.; Rozen, James R.; Steffen, Matthias, Removal of spurious microwave modes via flip-chip crossover.
  20. Nakashiba, Yasutaka, Semiconductor device having high-frequency interconnect.
  21. Chen,Kuei Shun; Lin,Chin Hsiang; Yen,Yung Sung; Lai,Chih Ming, Semiconductor device with scattering bars adjacent conductive lines.
  22. Farrar, Paul A., Subtractive metallization structure and method of making.
  23. Farrar, Paul A., Subtractive metallization structure with low dielectric constant insulating layers.
  24. Goebel, Thomas; Kaltalioglu, Erdem; Kim, Sun Oo, Support structures for semiconductor devices.
  25. Song, Jun-Ho; Park, Woon-Yong, Thin film transistor array panel for a liquid crystal display and methods for manufacturing the same.
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