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A semiconductor device having a high reliability passivation includes a planarization layer overlying a multi-level interconnect layer. The passivation layer has a planar surface upon which additional passivation layers are formed. Openings in the overlying passivation layers and the planarization l

A semiconductor device having a high reliability passivation includes a planarization layer overlying a multi-level interconnect layer. The passivation layer has a planar surface upon which additional passivation layers are formed. Openings in the overlying passivation layers and the planarization layer expose bonding pads in the multi-level interconnect layer. In a process for fabricating the device, the planarization layer is preferably formed by dispensing a siloxane spin-on-glass (SOG) material onto the surface of the multi-level interconnect layer. The SOG is subsequently planarized to form a substantially planar surface.

대표청구항 ▼

[ What is claimed is:] [1.]1. A method for forming a semiconductor device comprising the steps of:providing a semiconductor substrate having a plurality of patterned metal layers thereon, wherein each of the patterned metal layers is separated by a dielectric layer;forming a plasma oxide layer overl

[ What is claimed is:] [1.]1. A method for forming a semiconductor device comprising the steps of:providing a semiconductor substrate having a plurality of patterned metal layers thereon, wherein each of the patterned metal layers is separated by a dielectric layer;forming a plasma oxide layer overlying the plurality of patterned metal layers;forming a planarization layer overlying the plasma oxide layer;applying thermal energy to anneal the planarization layer;removing a portion of the planarization layer to form a substantially flat surface;hardening the planarization layer, after removing the portion of the planarization layer;forming a plasma oxide layer overlying the planarization layer; andforming a plasma nitride layer overlying the plasma oxide layer.