초록 ▼

A method for automatically generating a custom ESD network for an integrated circuit is provided. When a user provides chip size and chip capacitance for the integrated circuit, components for the customized ESD network are automatically selected based on the user-provided chip size and chip capacit

A method for automatically generating a custom ESD network for an integrated circuit is provided. When a user provides chip size and chip capacitance for the integrated circuit, components for the customized ESD network are automatically selected based on the user-provided chip size and chip capacitance and the adequacy of the ESD behavior of an ESD network employing the selected components is evaluated.

대표청구항 ▼

[ The invention claimed is:] [1.]1. A method of forming a customized ESD network for a circuit having a first, a second and a third power rail, the method comprising:providing a plurality of selectable elements for use within an ESD network;selecting at least a first resistor element and at least a

[ The invention claimed is:] [1.]1. A method of forming a customized ESD network for a circuit having a first, a second and a third power rail, the method comprising:providing a plurality of selectable elements for use within an ESD network;selecting at least a first resistor element and at least a first capacitor element from the plurality of selectable elements for use as a first RC discriminator network;selecting a first plurality of transistor elements from the plurality of selectable elements to form a first plurality of inverters for connecting to the first RC discriminator network;selecting a first transistor element from the plurality of selectable elements to form a first clamp for connecting to the first plurality of inverters and for connecting between the first and the third power rails;selecting at least a second resistor element and at least a second capacitor element from the plurality of selectable elements for use as a second RC discriminator network;selecting a second plurality of transistor elements from the plurality of selectable elements to form a second plurality of inverters for connecting to the second RC discriminator network;selecting a second transistor element from the plurality of selectable elements to form a second clamp for connecting to the second plurality of inverters and for connecting between the second and the third power rails; andselecting a plurality of diode elements from the plurality of selectable elements for connecting between the first and the second power rails for providing power-up sequence independence and power-down sequence independence between the first and second power rails.