$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method of forming metal interconnect structures and metal via structures using photolithographic and electroplating or electro-less plating procedures 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/476.3
출원번호 US-0310258 (1999-05-12)
발명자 / 주소
  • Lee Jin-Yuan,TWX
  • Wang Chen-Jong,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 20  인용 특허 : 35

초록

A process for forming metal interconnect structures, and metal via structures, using electroplating, or electroless plating procedures, has been developed. The process features the use of disposable conductive layers, used as seed layers for the plating procedures. After formation of the desired met

대표청구항

[ What is claimed is:] [1.]1. A method of fabricating metal interconnect structures, and metal via structures, on a semiconductor substrate, comprising the steps of:providing a first metal via structure, in a first insulator layer, with the top surface of the first metal via structure, exposed;depos

이 특허에 인용된 특허 (35)

  1. Battey James F. (Los Altos CA) Nelson Norvell J. (Palo Alto CA) Barnett Daniel J. (San Jose CA), Copper etching process and product.
  2. Polan Ned W. (Madison CT) Chao Chung-Yao (Hamden CT), Electrochemical treatment of copper for improving its bond strength.
  3. Ting Chiu H. (Saratoga CA) Paunovic Milan (Port Washington NY), Electroless deposition for IC fabrication.
  4. Schultz Paul B. (Farmington CT) Yarkosky Eugene F. (Milford CT), Electroless nickel plating of aluminum.
  5. Schultz Paul B. (Farmington CT) Yarkosky Eugene F. (Milford CT), Electroless nickel plating of aluminum.
  6. Curry ; II John W. (Austin TX) Yee Ian Y. K. (Austin TX), Fabrication of metal pillars in an electronic component using polishing.
  7. Maa Jer-shen (Plainsboro Township ; Middlesex County NJ), Formation of conductive lines.
  8. Crank Sue E. (Coppell TX), Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer.
  9. Havemann Robert H. ; Jeng Shin-Puu ; Gnade Bruce E. ; Cho Chih-Chen, Interconnect structure with an integrated low density dielectric.
  10. Stolk Richard D., Low loss magnetic alloy.
  11. Gulla Michael (Sherborn MA) Gaputis Charles A. (Hyde Park MA), Metal plating solution.
  12. Burch Robert R. (Exton PA), Metallized polymers.
  13. Burch Robert R. (Exton PA), Metallized polymers and method.
  14. Chakravorty Kishore K. (Issaquah WA) Tanielian Minas H. (Bellevue WA), Method for producing a planar surface on which a conductive layer can be applied.
  15. Polichette Joseph (South Farmingdale NY) Leech Edward J. (Oyster Bay NY), Method for the production of radiant energy imaged printed circuit boards.
  16. Sexton Richard W. (Grove City OH) Goddard David M. (Powell OH), Method of fabricating a fiber reinforced metal composite.
  17. Zhao Bin, Method of making a damascene metallization.
  18. Yee Ian Y. K. (Austin TX), Method of making a multilevel electrical airbridge interconnect.
  19. Kim Jong Oh,KRX ; Kim Sung Rae,KRX, Method of manufacturing a flash EEPROM cell.
  20. Sumitomo ; Yasusuke ; Ohashi ; Yoshie, Method of manufacturing semiconductor devices.
  21. Brighton Jeffrey E. (Katy TX) Roane Bobby A. (Manuel TX), Methods for forming self-aligned conductive pillars on interconnects.
  22. Chou William Tai-Hua (Cupertino CA) Wang Wen-chou Vincent (Cupertino CA), Methods of forming tall, high-aspect ratio vias and trenches in photo-imageable materials, photoresist materials, and th.
  23. Tingerthal Jeanne M. (Ramsey MN) Dado Gregory P. (Dane WI), Multi-chip substrate.
  24. Morishita Yasuyuki (Tokyo JPX), Multi-layer wiring structure in semiconductor device and method for manufacturing the same.
  25. Kumar Nalin (Austin TX) Lin Charles W. C. (San Antonio TX), Multilayer electrical interconnect fabrication with few process steps.
  26. Takahashi Hiroshi (Kasama JPX) Takanezawa Shin (Shimodate JPX) Kanno Masao (Shimodate JPX) Iwasaki Yorio (Shimodate JPX) Okamura Toshirou (Shimodate JPX) Nakaso Akishi (Oyama JPX) Hasegawa Kiyoshi (Y, Process for producing printed wiring board.
  27. Kelly Kimberley A. ; Malhotra Ashwani K. ; Perfecto Eric D. ; Yu Roy, Process for releasing a thin-film structure from a substrate.
  28. Polichette Joseph (South Farmingdale NY) Leech Edward J. (Oyster Bay NY) Nuzzi Francis J. (Freeport NY), Processes and products for making articles for electroless plating.
  29. Frisch David C. (Baldwin NY) Weber Wilhelm (Hicksville NY), Radiation stress relieving of polymer articles.
  30. Numata Ken (Dallas TX) Houston Kay L. (Richardson TX), Reliability of metal leads in high speed LSI semiconductors using dummy vias.
  31. De Bruin Leendert (Eindhoven NLX) Verhaar Robertus D. J. (Eindhoven NLX) Van Laarhoven Josephus M. F. G. (Eindhoven NLX), Selectively plating conductive pillars in manufacturing a semiconductor device.
  32. Cronin John Edward ; Kaanta Carter Welling, Self-aligned metallurgy.
  33. Nuzzi Francis J. (Lynbrook NY), Sensitized substrates for chemical metallization.
  34. Leibovitz Jacques (San Jose CA) Cobarruviaz Maria L. (Cupertino CA) Scholz Kenneth D. (Palo Alto CA) Chao Clinton C. (Redwood City CA), Stacked solid via formation in integrated circuit systems.
  35. Yu Chen-Hua,TWX ; Jang Syun-Ming,TWX ; Chen Chao-Cheng,TWX, VLSIC patterning process.

이 특허를 인용한 특허 (20)

  1. Claudio Brambilla IT; Manlio Sergio Cereda IT; Paolo Caprara IT, Method for autoaligning overlapped lines of a conductive material in integrated electronic circuits.
  2. Lee, Sung Gue; Kim, Yong Il; Jang, Yong Soon, Method for manufacturing a printed circuit board.
  3. McAvoy, Gregory John; Silverbrook, Kia, Method of forming connection between electrode and actuator in an inkjet nozzle assembly.
  4. Jung, Moon Youn; Jun, Chi Hoon, Method of forming photosensitive film pattern.
  5. McAvoy, Gregory John; Silverbrook, Kia, Method of forming thermal bend actuator with connector posts connected to drive circuitry.
  6. Daniel P. Labzentis ; Francesco F. Marconi ; Allan R. Knoll ; David J. Bajkowski, Method of producing flex circuit with selectively plated gold.
  7. McAvoy, Gregory John; Silverbrook, Kia, Printhead integrated circuit comprising inkjet nozzle assemblies having connector posts.
  8. McAvoy, Gregory John; Silverbrook, Kia, Printhead integrated circuit having connector posts encapsulated within nozzle chamber sidewalls.
  9. Trivedi, Jigish D., Semiconductor constructions.
  10. Aoyama,Junichi, Semiconductor device and method of manufacturing the same.
  11. Farrar, Paul A., Structures and methods to enhance copper metallization.
  12. Farrar, Paul A., Structures and methods to enhance copper metallization.
  13. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  14. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  15. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  16. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  17. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  18. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  19. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  20. Lin,Mou Shiung, Top layers of metal for high performance IC's.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로