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Method for forming a thin-film resistor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01C-017/06
출원번호 US-0191827 (1998-11-13)
발명자 / 주소
  • Lee Jia-Sheng,TWX
출원인 / 주소
  • United Microelectronics Corp., TWX
대리인 / 주소
    Wu
인용정보 피인용 횟수 : 52  인용 특허 : 8

초록

A method for forming a thin-film resistor includes forming two insulators on the thin-film resistor, forming contact holes by performing wet etching processes, and forming interconnect and contact plugs at the same time. The invention also provides another method for forming a thin-film resistor tha

대표청구항

[ What is claimed is:] [1.]1. A method for forming a thin-film resistor, comprising the steps of:providing a substrate having a first insulator disposed thereon;forming a thin-film resistor layer on the first insulator;patterning the thin-film resistor layer to form a thin-film,resistor;forming a se

이 특허에 인용된 특허 (8)

  1. Huang Cheng-Chung,TWX ; Chen Shu Mei,TWX, Automated method for monitoring and controlling the orthophosphoric acid etch rate of silicon nitride insulator layers.
  2. Mcquaid James G. (Mineral Wells TX) Bowlin Stanley L. (Weatherford TX), Layered film resistor with high resistance and high stability.
  3. Lee Joseph Y. (Agoura CA) Kriegel Michael H. (Santa Monica CA) Chuh Thomas Y. (Encinitas CA), Low noise polycrystalline semiconductor resistors by hydrogen passivation.
  4. Blanchard Richard A. (Los Altos CA), Manufacture of trimmable high value polycrystalline silicon resistors.
  5. Shibata Tadashi (Menlo Park CA), Method for manufacturing a semiconductor device.
  6. White Ted R. (Austin TX) Klein Jeff L. (Austin TX), Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide.
  7. Chan Lap (San Francisco CA) Sundaresan Ravis H. (Plano TX) Wei Che-Chia (Plano TX), Method of making back gate contact for silicon on insulator technology.
  8. Rao Raman K. (Palo Alto CA), Process enhancement using molybdenum plugs in fabricating integrated circuits.

이 특허를 인용한 특허 (52)

  1. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages having dual DMOS devices with power management integrated circuits.
  2. Lin, Mou-Shiung, Chip structure with a passive device and method for forming the same.
  3. Lin,Mou Shiung, Chip structure with redistribution traces.
  4. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
  5. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  6. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  7. Fivas, Joseph D.; Shah, Georgina; Chandler, Dianna L., Method for fabricating a thin film resistor semiconductor structure.
  8. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  9. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  10. Amadon,Jeffrey R.; Chinthakindi,Anil K.; Stein,Kenneth J.; Wong,Kwong H., Method of fabrication of thin film resistor with 0 TCR.
  11. Amadon, Jeffrey R.; Chinthakindi, Anil K.; Stein, Kenneth J.; Wong, Kwong H., Method of fabrication of thin film resistor with zero TCR.
  12. Lee, Jia-Sheng, Method of forming a thin-film resistor in a semiconductor wafer.
  13. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  14. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
  15. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  16. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  17. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.
  18. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  19. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  20. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  21. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  22. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  23. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  24. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
  25. Richter,Steffen; Nuernbergk,Dirk; Goettlich,Wolfgang, SOI contact structures.
  26. Ueno,Tohru, Semiconductor device.
  27. Lai,Zao Kuo; Wong,Lin Yin, Semiconductor package substrate with embedded resistors and method for fabricating the same.
  28. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  29. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  30. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  31. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  32. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  33. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  34. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  35. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  36. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  37. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  38. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  39. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  40. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  41. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  42. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  43. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  44. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  45. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  46. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  47. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  48. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  49. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  50. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  51. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.
  52. Lin, Mou-Shiung; Wei, Gu-Yeon, Voltage regulator integrated with semiconductor chip.
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