|국가/구분||United States(US) Patent 등록|
|미국특허분류(USC)||710/128 ; 710/125 ; 711/146|
|발명자 / 주소|
|출원인 / 주소|
|대리인 / 주소||
|인용정보||피인용 횟수 : 51 인용 특허 : 5|
A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues placed within address and data paths between the various controllers. The peripheral bus controller can decode a write cycle to memory, and the processor controller can thereafter request and be granted ownership of the CPU local bus. The address of the write cycle can then be snooped to determine if valid ...
[ What is claimed is:] [1.]1. A computer, comprising:a central processing unit (CPU) coupled to a CPU bus;a memory coupled to a memory bus;a peripheral device coupled to a peripheral bus; anda bus interface unit coupled between the CPU bus, the memory bus and the peripheral bus, wherein the bus interface unit is configured to obtain ownership of the CPU bus while forwarding a pre-defined number of snoop cycles upon the CPU bus, and wherein said pre-defined number of snoop cycles is established during reset of the computer.