초록 ▼

A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues placed within address and data paths between the

A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues placed within address and data paths between the various controllers. The peripheral bus controller can decode a write cycle to memory, and the processor controller can thereafter request and be granted ownership of the CPU local bus. The address of the write cycle can then be snooped to determine if valid data exists within the CPU cache storage locations. If so, a writeback operation can occur. Ownership of the CPU bus is maintained by the bus interface unit during the snooping operation, as well as during writeback and the request of the memory bus by the peripheral-derived write cycle. It is not until ownership of the memory bus is granted by the memory arbiter that mastership is terminated by the bus interface unit. Accordingly, the bus interface unit keeps CPU-derived cycles off the CPU bus to ensure memory arbiter grants ownership to a write cycle from the peripheral bus. In this fashion, data from the peripheral bus can be stored in system memory before accessing that data by a CPU read cycle. The number of snoop cycles which the bus interface unit can initiate is determined by configuration registers programmed during power on, reset or boot up of computer.

대표청구항 ▼

[ What is claimed is:] [1.]1. A computer, comprising:a central processing unit (CPU) coupled to a CPU bus;a memory coupled to a memory bus;a peripheral device coupled to a peripheral bus; anda bus interface unit coupled between the CPU bus, the memory bus and the peripheral bus, wherein the bus inte

[ What is claimed is:] [1.]1. A computer, comprising:a central processing unit (CPU) coupled to a CPU bus;a memory coupled to a memory bus;a peripheral device coupled to a peripheral bus; anda bus interface unit coupled between the CPU bus, the memory bus and the peripheral bus, wherein the bus interface unit is configured to obtain ownership of the CPU bus while forwarding a pre-defined number of snoop cycles upon the CPU bus, and wherein said pre-defined number of snoop cycles is established during reset of the computer.