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Method of manufacturing isolation trenches using silicon nitride liner 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/76
출원번호 US-0093383 (1998-06-08)
우선권정보 JP0156256 (1997-06-13)
발명자 / 주소
  • Ishikawa Hiraku,JPX
출원인 / 주소
  • NEC Corporation, JPX
대리인 / 주소
    Hayes, Soloway, Hennessey, Grossman & Hage, PC
인용정보 피인용 횟수 : 90  인용 특허 : 6

초록

In fabrication of a semiconductor device, firstly an isolation trench is formed on a substrate to isolate a plurality of semiconductor elements, and then a thermal oxide film is formed on a sidewall of the trench, whereupon a silicon oxide film is formed on the substrate by chemical vapor deposition

대표청구항

[ What is claimed is:] [1.]1. A method of manufacturing a semiconductor device, comprising the steps in sequence of:(a) forming on a substrate an isolation trench for isolating a plurality of semiconductor circuit elements;(b) forming a thermal oxide film on a sidewall of said isolation trench forme

이 특허에 인용된 특허 (6)

  1. Kishimoto Koji (Tokyo JPX) Homma Tetsuya (Tokyo JPX), Fabrication process for multilevel interconnections in a semiconductor device.
  2. Razouk Reda R. ; Egan Kulwant S. ; Yindeepol Wipawan ; Koscielniak Waclaw C., Method of forming an integrated circuit including filling and planarizing a trench having an oxygen barrier layer.
  3. Razouk Reda (Sunnyvale CA), Method of inducing flow or densification of phosphosilicate glass for integrated circuits.
  4. Chou George,TWX ; Chen Coming,TWX, Shallow trench isolation process.
  5. Bose Amitava (Nashua NH) Garver Marion M. (Marlborough MA) Nasr Andre I. (Marlborough MA) Cooperman Steven S. (Southborough MA), Shallow trench isolation process for high aspect ratio trenches.
  6. Jang Syun-Ming,TWX ; Chen Ying-Ho,TWX ; Yu Chen-Hua,TWX, Trench filling method employing oxygen densified gap filling silicon oxide layer formed with low ozone concentration.

이 특허를 인용한 특허 (90)

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