초록 ▼

An apparatus and method for decoding compressed digital video data which has been compressed, for example in a format compliant with the Motion Picture Experts Group I (MPEG) standard or the Joint Picture Experts Group (JPEG) standard. The apparatus and method allows a fast decoding rate for the com

An apparatus and method for decoding compressed digital video data which has been compressed, for example in a format compliant with the Motion Picture Experts Group I (MPEG) standard or the Joint Picture Experts Group (JPEG) standard. The apparatus and method allows a fast decoding rate for the compressed digital video data. A variable length decoding (VLD) circuit is used to generate a first bit sequence of a fixed length by decoding the received compressed digital video data. Then, an inverse quantizer is used to convert the first bit sequence by inverse quantization into a second bit sequence. A zig-zag buffer is then used to store the second bit sequence at specific locations and output a plurality of frequency-division binary signal bits concurrently in parallel. An inverse discrete cosine transfer (IDCT) circuit is used to process the plurality of frequency-division binary signal bits according to an inverse discrete cosine transfer function, to generate a plurality of time-division binary signal bits. These signal bits are combined into a time-division serial binary signal representative of decoded data for the compressed digital video data.

대표청구항 ▼

[ What is claimed is:] [1.]1. An apparatus for decoding a bit stream of compressed digital video data, comprising:(a) a variable length decoding (VLD) circuit, responsive to the compressed digital video data, for generating a first bit sequence of a fixed length by decoding the compressed digital vi

[ What is claimed is:] [1.]1. An apparatus for decoding a bit stream of compressed digital video data, comprising:(a) a variable length decoding (VLD) circuit, responsive to the compressed digital video data, for generating a first bit sequence of a fixed length by decoding the compressed digital video data;(b) an inverse quantizer, responsive to the generated first bit sequence, for converting the first bit sequence by an inverse quantization method into a second bit sequence;(c) a zig-zag buffer, responsive to the second bit sequence, for storing the second bit sequence at specific addresses and for generating a plurality of parallel frequency-division binary signal bits; and(d) an inverse discrete cosine transfer (IDCT) circuit, responsive to the plurality of parallel frequency-division binary signal bits, for processing the plurality of parallel frequency-division binary signal bits according to an inverse discrete cosine transfer function, to thereby generate a plurality of time-division binary signal bits, and for combining the time-division binary signal bits into a time-division serial binary signal representative of decoded data for the compressed digital video data.