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Scan path circuitry including a programmable delay circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
출원번호 US-0120678 (1998-07-21)
발명자 / 주소
  • Churchill Jonathan F.,GBX
  • Raftery Neil P.,GBX
  • Hendry Colin J.,GBX
  • Shanmugam Jeyakumar
  • Finn Mark A.
  • Surrette Thomas M.
  • Phelan Cathal G.
  • Pancholy Ashish
출원인 / 주소
  • Cypress Semiconductor Corporation
대리인 / 주소
    Wagner, Murabito & Hao LLP
인용정보 피인용 횟수 : 22  인용 특허 : 33

초록 ▼

A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a p

대표청구항

[ What is claimed is:] [11.]11. A method of delaying a signal, comprising:decoding a scan bit in a scan register; anddelaying the signal in response to decoding the scan bit.

이 특허에 인용된 특허 (33)

  1. Kim Gyu S. (Kyoungki-do KRX), Address transition detecting circuit of a semiconductor memory device.
    상세보기
  2. Roohparvar Frankie F. (Cupertino CA), Address transition detection (ATD) circuit.
    상세보기
  3. Han Gwang-Ma (Kyoungki KRX) Kim Gyu-Suk (Kyoungki KRX), Address transition detection circuit.
    상세보기
  4. Heyward Deborah J. (Hillsboro OR) Batz Joseph E. (Beaverton OR) Karnik Milind A. (Aloha OR) Frodsham R. Tim (Portland OR), Apparatus for generating a pulse clock signal for a multiple-stage synchronizer.
    상세보기
  5. Sud Rahul (Colorado Springs CO) Hardee Kim C. (Manitou Springs CO) Heightley John D. (Monument CO), Asynchronously equillibrated and pre-charged static ram.
    상세보기
  6. Chang Shuen-Chin (San Jose CA), CMOS power-on reset circuit.
    상세보기
  7. Sakashita Kazuhiro (Hyogo JPX) Tomioka Ichiro (Hyogo JPX) Hashizume Takeshi (Hyogo JPX), Circuit for transparent scan path testing of integrated circuit devices.
    상세보기
  8. Mao Robert S. (Hsinchu TWX), Circuit forming output pulse a selected delay after initiating pulse.
    상세보기
  9. Yamazaki Akira (Hyogo JPX) Kumanoya Masaki (Hyogo JPX) Konishi Yasuhiro (Hyogo JPX) Dosaka Katsumi (Hyogo JPX), Circuit having charge compensation and an operation method of the same.
    상세보기
  10. Shah Ashwin H. (Dallas TX), Constant pulse width generator.
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  11. Jiang Ching-Lin (Dallas TX) Podkowa William J. (Plano TX), Delay circuit for a monolithic integrated circuit and method for adjusting delay of same.
    상세보기
  12. Bertenshaw David R. (35 Ridgeway Close Lightwater ; Surrey GBX) Williamson Richard (35 Villiers Avenue Twickenham ; Middlesex ; TW2 6BL GBX) Wright John (58 Heathcroft Sunbury TW16 7TN GBX), Electric lighting and power controllers therefor.
    상세보기
  13. McClure David C. (Carrollton TX), Fuse circuitry to control the propagation delay of an IC.
    상세보기
  14. Reddy Chitranjan N. (Milpitas CA) Medhekar Ajit K. (San Jose CA), High-speed address transition detection circuit.
    상세보기
  15. Porter John D. (Austin TX) Branson Brian D. (Austin TX), Latching input buffer for an ATD memory.
    상세보기
  16. Dekker Robertus W. C. (Eindhoven NLX) Thijssen Aloysius P. (Pijnacker NLX) Beenker Franciscus P. M. (Eindhoven NLX) Jansen Joris F. P. (Eindhoven NLX), Memory device containing a static ram memory that is adapted for executing a self-test, and integrated circuit containin.
    상세보기
  17. Henri Jean-Claude (Boulogne Billancourt FRX) Andrieu Jean-Pierre (Paris FRX) Gault Dominique (Ville D\Avray FRX), Method for smoothing an image generated by coordinate conversion and a digital scan converter using the method.
    상세보기
  18. Childs Lawrence F. (Austin TX) Jones Kenneth W. (Austin TX) Flannagan Stephen T. (Austin TX) Chang Ray (Austin TX), Pipelined memory having synchronous and asynchronous operating modes.
    상세보기
  19. Ogawa Toshiyuki (Hyogo JPX) Kawai Shinji (Hyogo JPX), Power on reset circuit for semiconductor integrated circuit device.
    상세보기
  20. Ueda Chiharu (Tokyo JPX), Power-on clearing circuit in semiconductor IC.
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  21. Huott William V. (Wappingers Falls NY) McNamara Timothy G. (Fishkill NY), Programmable delay clock chopper/stretcher with fast recovery.
    상세보기
  22. Segawa Hiroshi (Itami JPX) Matsumura Tetsuya (Itami JPX), Pulse generating circuit in a semiconductor integrated circuit and a delay circuit therefor.
    상세보기
  23. Houston Theodore W. (Richardson TX), Pulse generator circuit and method.
    상세보기
  24. Hirano Hiroshige (Nara JPX) Taniguchi Takashi (Osaka JPX), Pulse signal generator and redundancy selection signal generator.
    상세보기
  25. Churchill Jonathan F.,GBX ; Raftery Neil P.,GBX ; Hendry Colin J.,GBX ; Shanmugam Jeyakumar ; Finn Mark A. ; Surrette Thomas M. ; Phelan Cathal G. ; Pancholy Ashish, Scan path circuitry including a programmable delay circuit.
    상세보기
  26. Miller Brent W. (Menlo Park CA) Walker William W. (Los Gatos CA) Cooke Laurence H. (San Jose CA), Scannable latch system and method.
    상세보기
  27. Stuebing Carlton (Tigard OR), Self-latching monostable circuit.
    상세보기
  28. Ito Tsuneo (Kodaira JPX), Semiconductor memory device.
    상세보기
  29. Obara Takashi (Tokyo JPX), Semiconductor memory device having diagnostic circuit for comparing multi-bit read-out test data signal with multi-bit w.
    상세보기
  30. Proebsting Robert J. (Los Altos CA), Speed enhancement technique for CMOS circuits.
    상세보기
  31. Ontrop Hans (Eindhoven NLX) Salters Roelof (Eindhoven NLX) Prince Betty (Eindhoven NLX) Davies Thomas J. (Eindhoven NLX) Phelan Cathal G. (Eindhoven NLX) O\Connell Cormac (Eindhoven NLX) Voss Peter H, Static memory unit having a plurality of test modes, and computer equipped with such units.
    상세보기
  32. Dingwall Andrew G. F. (Bridgewater NJ), Transition detector circuit.
    상세보기
  33. Pascucci, Luigi; Olivo, Marco, Zero-consumption power-on reset circuit.
    상세보기

이 특허를 인용한 특허 (22)

  1. Acharya,Yatin R; Bhat,Anand, Achieving desired synchronization at sequential elements while testing integrated circuits using sequential scan techniques.
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  2. Han, Sang-jib; Kim, Du-eung; Kwak, Choong-keun; Shin, Yun-seung, Integrated circuit capable of being burn-in tested using an alternating current stress and a testing method using the same.
    상세보기
  3. Sang-jib Han KR; Du-eung Kim KR; Choong-keun Kwak KR; Yun-seung Shin KR, Integrated circuit capable of being burn-in tested using an alternating current stress and a testing method using the same.
    상세보기
  4. Takaku, Kazuya; Honda, Yasufumi; Suzuki, Kenji, Memory control device.
    상세보기
  5. Barahmand, Mehrdad; Taheri, Saeed, Method and apparatus for adaptive clocking for boundary scan testing and device programming.
    상세보기
  6. Gorman, Kevin W.; Pontius, Dale E., Method and apparatus for implementing DRAM redundancy fuse latches using SRAM.
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  7. Doerr, Michael B.; Hallidy, William H.; Gibson, David A.; Chase, Craig M., Processing system with interspersed processors and communication elements having improved communication routing.
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  8. Doerr, Michael B.; Hallidy, William H.; Gibson, David A.; Chase, Craig M., Processing system with interspersed processors and communication elements having improved wormhole routing.
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  9. Doerr, Michael B.; Hallidy, William H.; Gibson, David A.; Chase, Craig M., Processing system with interspersed processors using selective data transfer through communication elements.
    상세보기
  10. Khanna, Sandeep, Programmable delay circuit within a content addressable memory.
    상세보기
  11. Khanna, Sandeep, Programmable delay circuit within a content addressable memory.
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  12. Khanna, Sandeep, Programmable delay circuit within a content addressable memory.
    상세보기
  13. Jue, Darren S.; Gupta, Ashish, Programmable delay elements for source synchronous link function design verification through simulation.
    상세보기
  14. Tkacik, Thomas; Daneshbeh, Amir, Securing proprietary functions from scan access.
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  15. Fagan, John L.; Bossard, Mark, Selectable delay pulse generator.
    상세보기
  16. Fernald, Kenneth W., Serial data interface.
    상세보기
  17. Chickanosky, Valarie H.; Gorman, Kevin W.; Granato, Suzanne; Ouellette, Michael R.; Pratt, Nancy H.; Ziegerhofer, Michael A., Staggered start of BIST controllers and BIST engines.
    상세보기
  18. Doerr, Michael B.; Hallidy, William H.; Gibson, David A.; Chase, Craig M., Stall propagation in a processing system with interspersed processors and communicaton elements.
    상세보기
  19. Pande,Anand; Ali,Syed Mohammed; Srinivas Koppineedi,Naresh Chandra; Bindus,Ravindra; Valmiki,Ramanujan K., System and apparatus for scanning integrated circuits with numerically controlled delay lines.
    상세보기
  20. Ramanathan, Girish P.; Rajappa, Srinivasan T., System for varying timing between source and data signals in a source synchronous interface.
    상세보기
  21. Versen,Martin; Nierle,Klaus; Kiehl,Oliver; Stahl,Ernst, Test mode method and apparatus for internal memory timing signals.
    상세보기
  22. Iyengar,Vinay; Nataraj,Bindiganavale S., Timing failure analysis in a semiconductor device having a pipelined architecture.
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