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A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conducti

A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.

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[ We claim:] [1.]1. A method of forming a flip chip package for an integrated circuit including the steps of:a. providing a semiconductor wafer containing a plurality of like integrated circuits, the semiconductor wafer having a front surface and an opposing rear surface, each of said integrated cir

[ We claim:] [1.]1. A method of forming a flip chip package for an integrated circuit including the steps of:a. providing a semiconductor wafer containing a plurality of like integrated circuits, the semiconductor wafer having a front surface and an opposing rear surface, each of said integrated circuits including a plurality of conductive bond pads formed upon the front surface of the semiconductor wafer for making electrical interconnections to each such integrated circuit;b. applying a layer of metal over the front surface of the semiconductor wafer;c. selectively removing portions of the applied metal layer over each of said integrated circuits to provide a patterned metal layer over each integrated circuit, each of such patterned metal layers providing a plurality of solder bump pads upon the front surface of each such integrated circuit, and each such patterned metal layer electrically coupling the conductive bond pads of each such integrated circuit to the solder bump pads of each such integrated circuit;d. applying a passivation layer over the front surface of the semiconductor wafer and above each of the patterned metal layers;e. forming openings in the applied passivation layer above each of the solder bump pads;f. applying ductile solder balls above each solder bump pad, each of said ductile solder balls having a generally spherical shape and measuring at least 9 mils (0.009 inch) in diameter, wherein the ductile solder balls have a characteristic reflow temperature at which they become molten;g. applying solder flux to the solder bump pads prior to application of the ductile solder balls;h. and thereafter heating the semiconductor wafer to the characteristic reflow temperature of such ductile solder balls after application of the solder flux and ductile solder balls to permanently secure such ductile solder balls to the solder bump pads; andi. dicing the semiconductor wafer following step h. to provide the plurality of integrated circuits in chip scale packaged form.