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Dynamic load balancing among processors in a parallel computer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/00
출원번호 US-0107933 (1998-06-30)
발명자 / 주소
  • Hardwick Jonathan C.,GBX
출원인 / 주소
  • Microsoft Corporation
대리인 / 주소
    Klarquist Sparkman Campbell Leigh & Whinston
인용정보 피인용 횟수 : 210  인용 특허 : 16

초록

A parallel programming system implements dynamic load balancing to distribute processing workload to available processors in a parallel computer. A preprocessor in the system converts a nested parallel program into sequential code executable on processors of the parallel computer and calls to a mess

대표청구항

[ I claim:] [1.]1. A method for dynamically balancing a processing workload among parallel processors operating on a program, where the program comprises recursive function calls capable of being executed in parallel, the method comprising:compiling both parallel and serial versions of the program,

이 특허에 인용된 특허 (16)

  1. Zaiki Koji (Kadoma JPX), Apparatus for detecting possibility of parallel processing and method thereof and a program translation apparatus utiliz.
  2. Fry Scott M. (Tucson AZ) Hempy Harry O. (Tucson AZ) Kittinger Bruce E. (Fort Collins CO), Balancing data-processing work loads.
  3. Mouradian Gary C., Data processing method and system utilizing parallel processing.
  4. Toyoda Koichi,JPX, Debugging method and debugging system for multi-task programs.
  5. Papadopoulos Gregory M. (Arlington MA), Efficient data processor instrumentation for systematic program debugging and development.
  6. Dubey Pradeep Kumar ; Barton Charles Marshall ; Chuang Chiao-Mei ; Lam Linh Hue ; O'Brien John Kevin ; O'Brien Kathryn Mary, Executing speculative parallel instructions threads with forking and inter-thread communication.
  7. Dias Daniel M. (Mahopac NY) Wolf Joel L. (Goldens Bridge NY) Yu Philip S. (Chappaqua NY), Joining two database relations on a common field in a parallel relational database field.
  8. Syre Jean-Claude (Munich DEX) Westphal Harald (Munich CA DEX) Hailperin Max (Hayward CA), Method and a system for processing logic programs.
  9. Kelley Michael ; Winner Stephanie, Method and apparatus for distributed interpolation of pixel shading parameter values.
  10. Blelloch Guy E. ; Gibbons Phillip B. ; Matias Yossi, Methods and means for scheduling parallel processors.
  11. Borrel Paul (Peekskill NY) Rossignac Jaroslaw R. (Ossining NY), Multi-resolution graphic representation employing at least one simplified model for interactive visualization applicatio.
  12. Ryu Tadamitsu (Kawasaki JPX) Ichikawa Naomi (Kawasaki JPX) Murakawa Masahiko (Kawasaki JPX) Toyota Masanobu (Kawasaki JPX) Adachi Takeshi (Kawasaki JPX), Object base data processing apparatus.
  13. Zaiki Koji (Osaka JPX), Processor scheduling method for iterative loops.
  14. Uchihira Naoshi,JPX ; Honiden Shinichi,JPX ; Ohsuga Akihiko,JPX ; Seki Toshibumi,JPX ; Nagai Yasuo,JPX ; Handa Keiichi,JPX ; Ito Satoshi,JPX ; Sawashima Nobuyuki,JPX ; Tahara Yasuyuki,JPX ; Shiotani , Programming method for concurrent programs and program supporting apparatus thereof.
  15. Harris Kevin W. (Nashua NH) Noyce William B. (Hollis NH), System and method for controlling execution of nested loops in parallel in a computer including multiple processors, and.
  16. Reeve Christopher L. (18 Salisbury Rd. Brookline MA 02146) Shavit Tani (One Seaborn Pl. Lexington MA 02173) Rothnie ; Jr. James B. (47 Monmouth St. Brookline MA 02146) Peters Timothy G. (11 Wilbur St, System for parallel processing that compiles a filed sequence of instructions within an iteration space.

이 특허를 인용한 특허 (210)

  1. Qureshi,Shiraz Ali, ACPI preprocessor.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  6. Lopez Estrada, Alex A., Adaptive configuration of platform.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  10. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  11. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  12. Grover, Vinod; Stratton, John A., Allocating memory for local variables of a multi-threaded program for execution in a single-threaded environment.
  13. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  14. Brenner, Larry Bert; Browning, Luke Matthew; Srinivas, Mysore Sathyanarayana; VanFleet, James William, Apparatus and method for initial load balancing in a multiple run queue system.
  15. Brenner, Larry Bert; Browning, Luke Matthew, Apparatus and method for periodic load balancing in a multiple run queue system.
  16. Brenner, Larry Bert; Browning, Luke Matthew, Apparatus and method for starvation load balancing using a global run queue in a multiple run queue system.
  17. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  18. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  19. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  20. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  21. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  22. Aguilar, Jr., Maximino; Day, Michael Norman; Nutter, Mark Richard; Stafford, James Michael, Asymmetric heterogeneous multi-threaded operating system.
  23. Minor, Barry L; Nutter, Mark Richard; To, VanDung Dang, Balancing computational load across a plurality of processors.
  24. Minor,Barry L; Nutter,Mark Richard; To,VanDung Dang, Balancing computational load across a plurality of processors.
  25. Archer, Charles J.; Faraj, Ahmad A., Broadcasting a message in a parallel computer.
  26. Archer, Charles J.; Faraj, Daniel A., Broadcasting a message in a parallel computer.
  27. Berg, Jeremy E.; Faraj, Ahmad A., Broadcasting a message in a parallel computer.
  28. Faraj, Ahmad, Broadcasting collective operation contributions throughout a parallel computer.
  29. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Collective operation protocol selection in a parallel computer.
  30. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Collective operation protocol selection in a parallel computer.
  31. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  32. Whitehill, Clifford A., Compiler independent bit-field macros.
  33. O'Brien, John Kevin Patrick; O'Brien, Kathryn M.; Prener, Daniel Arthur, Compiler method for employing multiple autonomous synergistic processors to simultaneously operate on longer vectors of data.
  34. Ruge,Thomas, Compression of streams of rendering commands.
  35. Imbert, Herve, Computational expansion system.
  36. Hayduk, Matthew A., Computing system capable of reducing power consumption by distributing execution of instruction across multiple processors and method therefore.
  37. Leiserson, Charles E.; Agrawal, Kunal; Hsu, Wen-Jing; He, Yuxiong, Computing the processor desires of jobs in an adaptively parallel scheduling environment.
  38. Conklin, Christopher R.; Philley, Randall W., Concurrent physical processor reassignment.
  39. Conklin,Christopher R.; Philley,Randall W., Concurrent physical processor reassignment method.
  40. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  41. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  42. Toub, Stephen; Ostrovsky, Igor; Duffy, Joe; Morrison, Vance; Yildiz, Huseyin, Controlling parallelization of recursion using pluggable policies.
  43. Archer, Charles Jens; Peters, Amanda; Ricard, Gary Ross; Sidelnik, Albert; Smith, Brian Edward, Database retrieval with a non-unique key on a parallel computer system.
  44. Archer, Charles J.; Carey, James E.; Sanders, Philip J.; Smith, Brian E., Developing collective operations for a parallel computer.
  45. Archer, Charles J.; Carey, James E.; Sanders, Philip J.; Smith, Brian E., Developing collective operations for a parallel computer.
  46. Orita, Ryuji; Arai, Susumu; Allison, Brian D.; Bland, Patrick M., Directing interrupts to currently idle processors.
  47. Kitamura,Manabu, Dynamic load balancing of a storage system.
  48. Lin, Weisi; Tye, Bee June; Ong, Ee Ping, Dynamic load-balancing between two processing means for real-time video encoding.
  49. Fuller, Nicholas C.; Li, Min; Meng, Shicong; Tan, Jian; Zeng, Liangzhao; Zhang, Li, Dynamic resource allocation in MapReduce.
  50. Brokenshire, Daniel Alan; Hofstee, Harm Peter; Minor, Barry L; Nutter, Mark Richard, Dynamically partitioning processing across a plurality of heterogeneous processors.
  51. Brokenshire,Daniel Alan; Hofstee,Harm Peter; Minor,Barry L; Nutter,Mark Richard, Dynamically partitioning processing across plurality of heterogeneous processors.
  52. Almasi, Gheorghe; Archer, Charles J.; Ratterman, Joseph D.; Smith, Brian E., Effecting a broadcast with an allreduce operation on a parallel computer.
  53. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Effecting hardware acceleration of broadcast operations in a parallel computer.
  54. Whitcomb, Thomas William; Lohia, Sumit, Elastic application framework for deploying software.
  55. Archer, Charles J.; Ratterman, Joseph D., Executing a gather operation on a parallel computer.
  56. Grover, Vinod; Aarts, Bastiaan Joannes Matheus; Murphy, Michael; Kolhe, Jayant B.; Pormann, John Bryan; Saylor, Douglas, Execution of retargetted graphics processor accelerated code by a general purpose processor.
  57. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  58. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  59. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  60. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  61. Aguilar, Jr., Maximino; Day, Michael Norman; Nutter, Mark Richard; Xenidis, James, Grouping processors and assigning shared memory space to a group in a heterogeneous computer environment.
  62. Arimilli, Lakshminarayana B.; Arimilli, Ravi K.; Rajamony, Ramakrishnan; Speight, William E., Hardware based dynamic load balancing of message passing interface tasks.
  63. Arimilli, Lakshminarayana B.; Arimilli, Ravi K.; Rajamony, Ramakrishnan; Speight, William E., Hardware based dynamic load balancing of message passing interface tasks by modifying tasks.
  64. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  65. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  66. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  67. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  68. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  69. Chung, I-Hsin; Klepacki, David J.; Lee, Che-Rung; Wen, Hui-Fang, Hierarchical task mapping.
  70. Arnold,Jeremy Alan; Barsness,Eric Lawrence; Dettinger,Richard Dean; Santosuosso,John Matthew, IDE integration with JDBC.
  71. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Improving efficiency of a global barrier operation in a parallel computer.
  72. Almasi, George; Cong, Guojing; Klepacki, David J.; Saraswat, Vijay A., Increasing parallel program performance for irregular memory access problems with virtual data partitioning and hierarchical collectives.
  73. Dutt, Bala; Kumar, Ajay; Susarla, Hanumantha R., Inducing concurrency in software code.
  74. Dean, Jeffrey; Ghemawat, Sanjay, Large-scale data processing in a distributed and parallel processing enviornment.
  75. Archer, Charles J.; Berg, Jeremy E.; Blocksome, Michael A.; Smith, Brian E., Line-plane broadcasting in a data communications network of a parallel computer.
  76. Archer, Charles J.; Berg, Jeremy E.; Blocksome, Michael A.; Smith, Brian E., Line-plane broadcasting in a data communications network of a parallel computer.
  77. Phull, Rajat; Cadambi, Srihari; Ravi, Nishkam; Chakradhar, Srimat, Load balancing on hetrogenous processing cluster based on exceeded load imbalance factor threshold determined by total completion time of multiple processing phases.
  78. Aguilar, Jr., Maximino; Chow, Alex Chunghen; Day, Michael Norman; Gowen, Michael Stan; Nutter, Mark Richard; Xenidis, James, Loading software on a plurality of processors.
  79. Aguilar, Jr.,Maximino; Chow,Alex Chunghen; Day,Michael Norman; Gowen,Michael Stan; Nutter,Mark Richard; Xenidis,James, Loading software on a plurality of processors.
  80. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  81. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  82. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  83. Aguilar, Jr., Maximino; Day, Michael Norman; Nutter, Mark Richard; Stafford, James Michael, Managing a plurality of processors as devices.
  84. Cypher, Robert E., Mechanism for increasing parallelization in computer programs with read-after-write dependencies associated with prefix operations.
  85. Vengerov, David, Method and apparatus for distributed state-based load balancing between task queues.
  86. Van Dyke, Korbin; Campbell, Paul W; Van Dyke, Don A.; Alasti, Ali; Purcell, Stephen C., Method and apparatus for dynamic allocation of processing resources.
  87. Van Dyke, Korbin; Campbell, Paul W; Van Dyke, Don A.; Alasti, Ali; Purcell, Stephen C., Method and apparatus for dynamic allocation of processing resources.
  88. Van Dyke, Korbin; Campbell, Paul; Van Dyke, Don A.; Alasti, Ali; Purcell, Stephen C., Method and apparatus for dynamic allocation of processing resources.
  89. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  90. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  91. Allen,Terry Dennis; Cheng,Hsiuying; Lin,Fen Ling; Shibamiya,Akira; Tsang,Annie S., Method and system for improving response time for database query execution.
  92. Doshi, Kedar; Fischer, Mark; Chou, Evan, Method and system for load balancing a sales forecast by selecting a synchronous or asynchronous process based on a type of event affecting the sales forecast.
  93. Doshi, Kedar; Fischer, Mark; Chou, Evan, Method and system for load balancing for determining a sales forecast by selecting a synchronous or asynchronous process based on a type of event affecting the sales forecast.
  94. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  95. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  96. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  97. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  98. Papaefstathiou, Efstathios, Method and system for predicting communication delays of detailed application workloads.
  99. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  100. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  101. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  102. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  103. Haller, Michael; Mitchell, Joan L.; Rijavec, Nenad; Smith, II, James T., Method and system for task mapping to iteratively improve task assignment in a heterogeneous computing system.
  104. Tellez, Juan; Dageville, Benoit, Method for computing the degree of parallelism in a multi-user environment.
  105. Brenner,Larry Bert; Browning,Luke Matthew, Method for determining idle processor load balancing in a multiple processors system.
  106. Beaumont,Mark, Method for finding global extrema of a set of bytes distributed across an array of parallel processing elements.
  107. Beaumont, Mark, Method for finding global extrema of a set of shorts distributed across an array of parallel processing elements.
  108. Beaumont,Mark, Method for finding local extrema of a set of values for a parallel processing element.
  109. Beaumont,Mark, Method for load balancing a line of parallel processing elements.
  110. Beaumont,Mark, Method for load balancing a loop of parallel processing elements.
  111. Beaumont,Mark, Method for load balancing an n-dimensional array of parallel processing elements.
  112. Bhagat, Suneel; Risner, David A., Method for managing user and server applications in a multiprocessor computer system.
  113. Beaumont, Mark, Method for manipulating data in a group of processing elements according to locally maintained counts.
  114. Beaumont, Mark, Method for manipulating data in a group of processing elements to perform a reflection of the data.
  115. Beaumont,Mark, Method for manipulating data in a group of processing elements to transpose the data using a memory stack.
  116. Beaumont,Mark, Method for rounding values for a plurality of parallel processing elements.
  117. Beaumont,Mark, Method for using extrema to load balance a loop of parallel processing elements.
  118. Beaumont,Mark, Method for using filtering to load balance a loop of parallel processing elements.
  119. Beaumont,Mark, Method of obtaining interleave interval for two data values.
  120. Beaumont, Mark, Method of rotating data in a plurality of processing elements.
  121. Beaumont, Mark, Method of shifting data along diagonals in a group of processing elements to transpose the data.
  122. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  123. Choy, Long Yin; Edelman, Alan; Husbands, Parry Jones Reginald, Methods and apparatus for parallel execution of a process.
  124. Arimilli, Lakshminarayana B.; Arimilli, Ravi K.; Rajamony, Ramakrishnan; Speight, William E., Modifying an operation of one or more processors executing message passing interface tasks.
  125. Son, Min Young; Lee, Shi Hwa; Lee, Seung Woo; Shin, Young Sam, Multi-core system and method for processing data in parallel in multi-core system.
  126. Hokenek, Erdem; Moudgill, Mayan; Glossner, C. John, Multithreaded processor with efficient processing for convergence device applications.
  127. Bunker, V,Nelson Waldo; Laizerovich,David; Bunker,Eva Elizabeth; Van Schuyver,Joey Don, Network security testing.
  128. Mealey, Bruce G.; Mewhinney, Greg R.; Srinivas, Mysore S.; Warrier, Suresh E., Offloading input/output (I/O) completion operations.
  129. Mealey, Bruce G.; Mewhinney, Greg R.; Srinivas, Mysore S.; Warrier, Suresh E., Offloading input/output (I/O) completion operations.
  130. Blumrich,Matthias A.; Chen,Dong; Gara,Alan G.; Giampapa,Mark E.; Heidelberger,Philip; Steinmacher Burow,Burkhard D.; Vranas,Pavlos M., One-bounce network.
  131. Archer, Charles J.; Carey, James E.; Markland, Matthew W.; Sanders, Philip J., Optimizing collective operations.
  132. Jain, Anket; Ramalingam, Ramkumar; Ravi, Lohith; VenkataKrishnan, S., Parallel access of partially locked content of input file.
  133. Gulko,Abraham; Mellor,David, Parallel computing system, method and architecture.
  134. Yildiz, Huseyin S.; Toub, Stephen S.; Ringseth, Paul; Duffy, John, Parallel execution of a loop.
  135. Jia, Bin, Parallel pipelined vector reduction in a data processing system.
  136. Hirooka, Takashi; Ohta, Hiroshi; Iitsuka, Takayoshi; Kikuchi, Sumio, Parallel program generating method.
  137. Archer, Charles J.; Peters, Amanda; Ricard, Gary R.; Sidelnik, Albert; Smith, Brian E., Parallel-prefix broadcast for a parallel-prefix operation on a parallel computer.
  138. Grover, Vinod; Aarts, Bastiaan Joannes Matheus; Murphy, Michael, Partitioning CUDA code for execution by a general purpose processor.
  139. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Performing a deterministic reduction operation in a compute node organized into a branched tree topology.
  140. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Performing a deterministic reduction operation in a parallel computer.
  141. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Performing a deterministic reduction operation in a parallel computer.
  142. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Performing a global barrier operation in a parallel computer.
  143. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Performing a local barrier operation.
  144. Blocksome, Michael A.; Faraj, Daniel A., Performing a local reduction operation on a parallel computer.
  145. Blocksome, Michael A.; Faraj, Daniel A., Performing a local reduction operation on a parallel computer.
  146. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Performing a scatterv operation on a hierarchical tree network optimized for collective operations.
  147. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Performing a vector collective operation on a parallel computer having a plurality of compute nodes.
  148. Archer, Charles J.; Peters, Amanda E.; Smith, Brian E., Performing an all-to-all data exchange on a plurality of data buffers by performing swap operations.
  149. Archer, Charles J.; Peters, Amanda E.; Smith, Brian E., Performing an all-to-all data exchange on a plurality of data buffers by performing swap operations.
  150. Faraj, Ahmad, Performing an allreduce operation on a plurality of compute nodes of a parallel computer.
  151. Faraj, Ahmad, Performing an allreduce operation on a plurality of compute nodes of a parallel computer.
  152. Faraj, Ahmad, Performing an allreduce operation on a plurality of compute nodes of a parallel computer.
  153. Archer, Charles J.; Dozsa, Gabor; Ratterman, Joseph D.; Smith, Brian E., Performing an allreduce operation using shared memory.
  154. Le Grand, Scott M., Performing an occurence count of radices.
  155. Arimilli, Lakshminarayana B.; Arimilli, Ravi K.; Rajamony, Ramakrishnan; Speight, William E., Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks.
  156. Arimilli, Lakshminarayana B.; Arimilli, Ravi K.; Rajamony, Ramakrishnan; Speight, William E., Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks.
  157. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Processing communications events in parallel active messaging interface by awakening thread from wait state.
  158. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Processing data communications events by awakening threads in parallel active messaging interface of a parallel computer.
  159. Gootherts, Paul; Larson, Douglas V., Processing thread launching using volunteer information.
  160. Aguilar, Jr., Maximino; Nutter, Mark Richard; Stafford, James Michael, Processor dedicated code handling in a multi-processor environment.
  161. Aguilar, Jr., Maximino; Nutter, Mark Richard; Stafford, James Michael, Processor dedicated code handling in a multi-processor environment.
  162. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  163. Le Grand, Scott M., Reordering data using a series of offsets.
  164. Hohensee, Paul H., Resource utilization monitor.
  165. Grover, Vinod; Aarts, Bastiaan Joannes Matheus; Murphy, Michael; Beylin, Boris; Kolhe, Jayant B.; Saylor, Douglas, Retargetting an application program for execution by a general purpose processor.
  166. Yamashita,Koichiro, Scheduling apparatus performing job scheduling of a parallel computer system.
  167. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Send-side matching of data communications messages.
  168. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Send-side matching of data communications messages.
  169. Blocksome, Michael; Dozsa, Gabor; Gooding, Thomas M.; Heidelberger, Philip; Kumar, Sameer; Mamidala, Amith R.; Miller, Douglas, Shared address collectives using counter mechanisms.
  170. Ali, Shoukat; Katrinis, Konstantinos; Schenfeld, Eugen; Li, Cheng-hong; Park, Alfred; Ajwani, Deepak, Simulating stream computing systems.
  171. Master,Paul L.; Watson,John, Storage and delivery of device features.
  172. Sathyanarayana, Karthik; DiVincenzo, Jonathan; Feng, Jie, Stream publishing and distribution capacity testing.
  173. Pike, Robert C.; Quinlan, Sean; Dorward, Sean M.; Dean, Jeffrey; Ghemawat, Sanjay, System and method for analyzing data records.
  174. Dutt,Bala; Kumar,Ajay; Susarla,Hanumantha R., System and method for block-based concurrentization of software code.
  175. Dean, Jeffrey; Ghemawat, Sanjay, System and method for efficient large-scale data processing.
  176. Dutt,Bala; Kumar,Ajay; Susarla,Hanumantha R., System and method for goal-based scheduling of blocks of code for concurrent execution.
  177. Aguilar, Jr.,Maximino; Day,Michael Norman; Nutter,Mark Richard; Xenidis,James, System and method for grouping processors and assigning shared memory space to a group in heterogeneous computer environment.
  178. Arbouzov,Leonid M.; Bobrovsky,Konstantin S., System and method for java preprocessor.
  179. Dean, Jeffrey; Ghemawat, Sanjay, System and method for large-scale data processing using an application-independent framework.
  180. Dean, Jeffrey; Ghemawat, Sanjay, System and method for large-scale data processing using an application-independent framework.
  181. Malewicz, Grzegorz; Dvorsky, Marian; Colohan, Christopher B.; Thomson, Derek P.; Levenberg, Joshua Louis, System and method for limiting the impact of stragglers in large-scale parallel data processing.
  182. Malewicz, Grzegorz; Dvorsky, Marian; Colohan, Christopher B.; Thomson, Derek P.; Levenberg, Joshua Louis, System and method for limiting the impact of stragglers in large-scale parallel data processing.
  183. Malewicz, Grzegorz; Dvorsky, Marian; Colohan, Christopher B.; Thomson, Derek P.; Levenberg, Joshua Louis, System and method for limiting the impact of stragglers in large-scale parallel data processing.
  184. Malewicz, Grzegorz; Dvorsky, Marian; Colohan, Christopher B.; Thomson, Derek P.; Levenberg, Joshua Louis, System and method for limiting the impact of stragglers in large-scale parallel data processing.
  185. Dutt, Bala; Kumar, Ajay; Susarla, Hanumantha R., System and method for marking software code.
  186. Burlacu-Zane, Anca Gabriela; Zaafrani, Abderrazek, System and method for modulo addressing vectorization with invariant code motion.
  187. Aguilar, Jr.,Maximino; Craft,David; Day,Michael Norman; Hatakeyama,Akiyuki; Hofstee,Harm Peter; Suzuoki,Masakazu, System and method for selecting and using a signal processor in a multiprocessor system to operate as a security for encryption/decryption of data.
  188. Gordy, Robert Stephen; Spitzer, Terry, System and method for the distribution of a program among cooperating processing elements.
  189. Gordy, Robert Stephen; Spitzer, Terry, System and method for the distribution of a program among cooperating processing elements.
  190. Gordy, Robert Stephen; Spitzer, Terry, System and method for the distribution of a program among cooperating processors.
  191. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  192. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  193. Nils Nieuwejaar, System for facilitating remote access to parallel file system in a network using priviliged kernel mode and unpriviliged user mode to avoid processing failure.
  194. Brenner,Larry Bert; Browning,Luke Matthew, System for preventing periodic load balancing if processor associated with lightest local run queue has benefited from idle processor load balancing within a determined time period.
  195. Beaumont, Mark, System of rotating data in a plurality of processing elements.
  196. Agarwal, Shivali; Narang, Ankur; Shyamasundar, Rudrapatna K., Systems and methods for affinity driven distributed scheduling of parallel computations.
  197. Bikshandi, Ganesh; Venkata, Krishna Nandivada; Peshansky, Igor; Saraswat, Vijay Anand, Systems and methods for automatically optimizing high performance computing programming languages.
  198. Takada, Aritoki, Systems and methods for managing public and private queues for a storage system.
  199. Levanoni,Yossi; Saha,Sanjib; Mehta,Bimal Kumar; Maybee,Paul; Graber,Lee; Sriram,Balasubramanian; Musayev,Eldar Azerovich; Smith,Kevin Bowen, Systems and methods for using metrics to control throttling and swapping in a message processing system.
  200. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  201. Brokenshire,Daniel Alan; Day,Michael Norman; Minor,Barry L; Nutter,Mark Richard; To,VanDung Dang, Task queue management of virtual devices using a plurality of processors.
  202. Garth,John Marland; Ruddy,James Alan; Shibamiya,Akira, Technique for determining an optimal number of tasks in a parallel database loading system with memory constraints.
  203. Peterson,Ricky Merle, Thread dispatch for multiprocessor computer systems.
  204. Grover, Vinod; Aarts, Bastiaan Joannes Matheus; Murphy, Michael, Thread-local memory reference promotion for translating CUDA code for execution by a general purpose processor.
  205. Ruge, Thomas, Transparency-conserving system, method and computer program product to generate and blend images.
  206. Levanoni, Yossi; Saha, Sanjib; Mehta, Bimal Kumar; Maybee, Paul; Graber, Lee; Sriram, Balasubramanian; Musayev, Eldar Azerovich; Smith, Kevin Bowen, Use of metrics to control throttling and swapping in a message processing.
  207. Nguyen, Trung N.; Rasor, Louis A.; Ruiz, Juan J., Using send buffers and receive buffers for sending messages among nodes in a network.
  208. Grover, Vinod; Aarts, Bastiaan Joannes Matheus; Murphy, Michael, Variance analysis for translating CUDA code for execution by a general purpose processor.
  209. Brokenshire,Daniel Alan; Day,Michael Norman; Minor,Barry L; Nutter,Mark Richard, Virtual devices using a pluarlity of processors.
  210. Brokenshire, Daniel Alan; Day, Michael Norman; Minor, Barry L; Nutter, Mark Richard, Virtual devices using a plurality of processors.
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