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Method of forming multi-level coplanar metal/insulator films using dual damascene with sacrificial flowable oxide 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0884861 (1997-06-30)
발명자 / 주소
  • Feldner Klaus,DEX
  • Grewal Virinder,DEX
  • Vollmer Bernd
  • Schnabel Rainer Florian
출원인 / 주소
  • Siemens Aktiengesellschaft, DEX
대리인 / 주소
    Braden
인용정보 피인용 횟수 : 32  인용 특허 : 5

초록

An improved method of performing a dual damascene etch through a layer stack disposed above a substrate. The layer stack includes an underlying device layer and an insulating layer disposed above the underlying device layer. The method includes forming a trench in a top surface of the insulating lay

대표청구항

[ What is claimed is:] [1.]1. A method of performing a dual damascene etch through a layer stack comprising an underlying device layer, an insulating layer disposed above said underlying device layer, said method comprising:forming a trench in a top surface of said insulating layer, said trench bein

이 특허에 인용된 특허 (5)

  1. Joly, Alison; Schreiner, George F.; Stanton, Lawrence W.; White, R. Tyler, Agonists and antagonists of peripheral-type benzodiazepine receptors.
  2. Lee Seung-ku (Kwangmyeong KRX) Oh Kyung-seok (Suwon KRX), Method for forming contact holes having different depths.
  3. Hong Gary (Hsin Chu TWX) Huang Cheng H. (Hsin Chu TWX) Yang Ming-Tzong (Hsin Chu TWX) Pan Hong-Tsz (Chang-hua TWX), Process for contact hole formation using a sacrificial SOG layer.
  4. Tanaka Toshihiko,JPX ; Uchino Shoichi,JPX ; Asai Naoko,JPX, Resist pattern forming method using anti-reflective layer, resist pattern formed, and method of etching using resist pa.
  5. Avanzino Steven (Cupertino CA) Gupta Subhash (San Jose CA) Klein Rich (Mountain View CA) Luning Scott D. (Menlo Park CA) Lin Ming-Ren (Cupertino CA), Self aligned via dual damascene.

이 특허를 인용한 특허 (32)

  1. Riess, Philipp; Kaltalioglu, Erdem; Wendt, Hermann, Devices formed with dual damascene process.
  2. Chen, Meng-Hung; Shu, Yu-Sheng; Lo, Ming Hung; Lee, Chung-Yuan, Dual damascene process.
  3. Riess, Philipp; Kaltalioglu, Erdem; Wendt, Hermann, Dual damascene process.
  4. Chen, Chao Cheng; Yeh, Chen Nan; Fu, Chien Chung, Dual damascene process flow for porous low-k materials.
  5. MacIntyre,Donald M., Hermetic wafer scale integrated circuit structure.
  6. MacIntyre,Donald M., Hermetic wafer scale integrated circuit structure.
  7. Hui, Angela T.; Ramsbey, Mark T.; Sun, Yu; Matsumoto, David H., Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation.
  8. Armacost, Mike; Spuler, Bruno; Brase, Gabriela; Gutmann, Alois, Method for forming dual damascene structure.
  9. Fei Wang ; Lynne A. Okada ; Ramkumar Subramanian ; Calvin T. Gabriel, Method for making a slot via filled dual damascene low k interconnect structure without middle stop layer.
  10. Chen, Chun-Che; Wang, Tza-Hao, Method of deep contact fill and planarization for dual damascene structures.
  11. Sun, Yu-Chi; Huang, Tse-Yao, Method of fabricating bit line and bit line contact plug of a memory cell.
  12. Shea, Kevin; Busch, Brett; Good, Farrell; Vasilyeva, Irina; Bhat, Vishwanath, Method of forming capacitors.
  13. Jun, Jin-Won; Kim, Young-Wug; Park, Tae-Soo; Lee, Kyung-Tae, Method of forming dual damascene interconnection using low-k dielectric.
  14. Kim,Jae Hak; Lee,Soo Geun; Park,Ki Kwan; Lee,Kyoung Woo, Method of forming dual damascene interconnection using low-k dielectric material.
  15. MacIntyre,Donald M., Method of forming hermetic wafer scale integrated circuit structure.
  16. Hidenori Shibata JP, Method of manufacturing a multi-layered wiring structure for interconnecting semiconductor devices by patterning resist and antireflective films to define wiring grooves.
  17. Kiehlbauch, Mark; Shea, Kevin, Methods of forming capacitors.
  18. Kiehlbauch, Mark; Shea, Kevin R., Methods of forming capacitors.
  19. Kiehlbauch, Mark; Shea, Kevin R., Methods of forming capacitors.
  20. Shea, Kevin; Busch, Brett; Good, Farrell; Vasilyeva, Irina; Bhat, Vishwanath, Methods of forming capacitors.
  21. Michael S. Nashner ; Bruce Beattie, Post etch clean sequence for making a semiconductor device.
  22. Wang, Fei; Okada, Lynne A.; Subramanian, Ramkumar; Gabriel, Calvin T., Slot via filled dual damascene interconnect structure without middle etch stop layer.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  28. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  29. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  30. MacIntyre, Donald Malcolm, Wafer scale method of packaging integrated circuit die.
  31. MacIntyre,Donald Malcolm, Wafer scale semiconductor structure.
  32. Brase, Gabriela; Schroeder, Uwe Paul; Holloway, Karen Lynne, `Via first` dual damascene process for copper metallization.
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