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특허 상세정보

MyON담기
내보내기 페이스북 공유 카카오톡 공유

Edge connectable metal package

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H01L-023/495   
미국특허분류(USC) 257/666 ; 257/704 ; 257/692
출원번호 US-0435237 (1995-05-05)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Rosenblatt
인용정보 피인용 횟수 : 28  인용 특허 : 29
초록

There is provided an edge connectable electronic package. The package has a metallic base at least partially coated with a dielectric layer. An interconnection means taking the form of either a leadframe or a circuit trace is electrically interconnected to an encased semiconductor device. The opposing end of the interconnection means extends to the package perimeter for interconnection to a socket or brazing to external leads.

대표
청구항

[ What is claimed is:] [1.]1. A package for encasing one or more electronic devices, comprising:a base component having a first perimeter;a cover component having a second perimeter of a size less than said first perimeter; anda leadframe disposed between and bonded to the base component and the cover component, said leadframe having an external portion that extends beyond said second perimeter, terminates adjacent to said first perimeter and rigidly adheres to said base component.

이 특허에 인용된 특허 (29)

  1. Mahulikar Deepak (Meriden CT) Popplewell James M. (Guilford CT). Aluminum alloy semiconductor packages. USP1990074939316.
  2. Maeda Ryu (Tokyo JPX) Fukuoka Shingoro (Tokyo JPX) Yatabe Hiroshi (Yokohama JPX). Aluminum enamel board. USP1989064842959.
  3. Ohashi Toshio (Komaki JPX) Wakayama Masaki (Kasugai JPX). Ceramic package for memory semiconductor. USP1993105256901.
  4. Butt Sheldon H. (Godfrey IL). Chip carrier. USP1989084862323.
  5. Smolko Gennady G. (103482 korpus 501 ; kv. 19 Moscow SUX). Electronic device. USP1980024188652.
  6. SinghDeo Narendra N. (New Haven CT) Mahulikar Deepak (Meriden CT) Butt Sheldon H. (Godfrey IL). Electronic packaging of components incorporating a ceramic-glass-metal composite. USP1989114882212.
  7. Voss Scott V. (Portola Valley CA). Heat dissipating interconnect tape for use in tape automated bonding. USP1989054827376.
  8. Dtzer Richard (Nuremberg DEX) Lechner Ernst-Friedrich (Erlangen DEX). Heat-removing circuit boards. USP1985014495378.
  9. Butt Sheldon H. (Godfrey IL). Hermetic microminiature packages. USP1990104967260.
  10. Hascoe ; Norman. Hermetically sealed container for semiconductor and other electronic device s. USP1978084105861.
  11. Rothgery Eugene F. (No. Branford CT) Hart William W. C. (Bethany CT) Smith ; III Edward F. (Madison CT) Phillips Steven D. (Northford CT) Sandel Bonnie B. (Milford CT) Gavin David F. (Cheshire CT). Metal electronic package sealed with thermoplastic having a grafted metal deactivator and antioxidant. USP1989034812896.
  12. Butt Sheldon H. (Godfrey IL) Mahulikar Deepak (Meriden CT). Metal packages having improved thermal dissipation. USP1990104961106.
  13. Nakahashi Masako (Kawasaki JPX) Shirokane Makoto (Tokyo JPX) Yamazaki Tatsuo (Tokyo JPX) Yoshino Hisashi (Yokohama JPX) Hori Akio (Kawasaki JPX) Takeda Hiromitsu (Tokyo JPX). Method for preparing highly heat-conductive substrate and copper wiring sheet usable in the same. USP1986094611745.
  14. McMonagle Rodger P. (Tempe AZ). Microwave circuit boards. USP1986124633035.
  15. Kovacs Alan L. (Long Beach CA) Johnson Gary W. (Irvine CA) Vitriol William A. (Anaheim CA) Shock ; Jr. Clifford L. (San Luis Obispo CA). Pre-stressed laminated lid for electronic circuit package. USP1993125268533.
  16. Minten Karl L. (Cannock NJ GBX) Pismennaya Galina (Palisades Park NJ). Process for preparing a non-conductive substrate for electroplating. USP1986104619741.
  17. Pasqualoni Anthony M. (Hamden CT) Mahulikar Deepak (Meriden CT) Jalota Satish K. (Wallingford CT) Brock Andrew J. (Cheshire CT). Process for producing black integrally colored anodized aluminum components. USP1991115066368.
  18. Butt Sheldon H. (Godfrey IL). Semiconductor casing. USP1984074461924.
  19. Cherukuri Satyam C. (West Haven CT) Butt Sheldon H. (Godfrey IL). Semiconductor casing. USP1989014796083.
  20. Hidaka Norio (Sagamihara JPX) Yamamura Shigeyuki (Sagamihara JPX) Fukuta Masumi (Machida JPX). Semiconductor device. USP1990034908694.
  21. Kaiser ; Jr. Joseph A. (Framingham MA) Hewitt Bert S. (Acton MA). Semiconductor device package and packaging method. USP1990084953001.
  22. Kaneda Kenichi (Tokyo JPX) Tanda Akio (Tokyo JPX). Semiconductor device package having a low profile structure and high strength. USP1994045302852.
  23. Kobayashi Kenzi (Tokyo JPX) Mori Hajime (Tokyo JPX) Yamaguti Yukio (Tokyo JPX). Semiconductor device package having locating mechanism for properly positioning semiconductor device within package. USP1994055311402.
  24. Katayama Shigeru (Sodegaura JPX) Tominaga Kaoru (Sodegaura JPX) Yoshitake Junichi (Sodegaura JPX). Semiconductor device with an airtight space formed internally within a hollow package. USP1994085343076.
  25. Butt Sheldon H. (Godfrey IL). Semiconductor package. USP1991055014159.
  26. Crane Jacob (Woodbridge CT) Johnson Barry C. (Tucson AZ) Mahulikar Deepak (Meriden CT) Butt Sheldon H. (Godfrey IL). Semiconductor package. USP1989124888449.
  27. Butt Sheldon H. (Godfrey IL). Semiconductor packaging. USP1989064839716.
  28. Sukonnik Israil M. (Plainville MA) Forster James A. (Barrington RI) Breit Henry F. (Attleboro MA) Raphanella Gary A. (South Easton MA). Substrate for an electrical circuit system and a circuit system using that substrate. USP1991105055967.
  29. Doi Yoshihiko (Hyogo JPX) Ogasa Nobuo (Hyogo JPX) Ohtsuka Akira (Hyogo JPX) Igarashi Tadashi (Hyogo JPX). Substrate for use in semiconductor apparatus. USP1984104480013.

이 특허를 인용한 특허 피인용횟수: 28

  1. Boon, Suan Jeung. Adhesive layer for an electronic apparatus having multiple semiconductor devices. USP2004036710454.
  2. Lee,Shaw Wei; Tu,Nghia Thuc; Nadarajah,Santhiran S/O; Soon,Lim Peng. Apparatus and method for miniature semiconductor packages. USP2008097419855.
  3. Lee,Shaw Wei; Tu,Nghia Thuc; Nadarajah,Santhiran S/O; Soon,Lim Peng. Apparatus and method for miniature semiconductor packages. USP2007017161232.
  4. Hooper, Stephen R.; Bowles, Philip H.. Cavity-type semiconductor package and method of packaging same. USP2016019227838.
  5. Hooper, Stephen R.; Bowles, Philip H.. Cavity-type semiconductor package and method of packaging same. USP2014128906747.
  6. Sekowski, Daniel; Carpenter, Frederick Lloyd; Hand, Mark Anthony; Bachl, Bernhard; Bienek, Bernd; Cladders, Olaf; Dieker, Henning; Miesner, Christian; Schopmann, Lothar; Zimmer, Herfried. Electronic apparatus having an encapsulating layer within and outside of a molded frame overlying a connection arrangement on a circuit board. USP2012058184440.
  7. Punzalan, Jefferey D.; Tan, Hien Boon; Zheng, Zheng; Yee, Jae Hak; Han, Byung Joon. Ground plane for exposed package. USP2005046876069.
  8. Punzalan, Jeffrey D.; Tan, Hien Boon; Zheng, Zheng; Yee, Jae Hak; Han, Byung Joon. Ground plane for exposed package. USP2003106630373.
  9. Takagi, Kazutaka. High frequency package device with internal space having a resonant frequency offset from frequency used. USP2011027888797.
  10. Evans,Robert D.; Bronson,David. Hydrogen diffusion hybrid port and method of making. USP2007047205179.
  11. Douglas, Edward C.. Integrated circuit chip package. USP2004056730991.
  12. Liu, Jwei Wien; O'Connor, John P.. Masking layer in substrate cavity. USP2005046876071.
  13. Liu,Jwei Wien; O'Connor,John P.. Masking layer in substrate cavity. USP2008017314816.
  14. Sekowski, Daniel; Carpenter, Frederick Lloyd; Hand, Mark Anthony; Bachl, Bernhard; Bienek, Bernd; Cladders, Olaf; Dieker, Henning; Miesner, Christian; Schopmann, Lothar; Zimmer, Herfried. Method for making an electronic apparatus having an encapsulating layer within and outside of a molded frame overlying a connection arrangement on a circuit board. USP2015089105819.
  15. Reichert,Hans J��rg; Deckers,Margarete; Zanner,Rainer. Method for producing a chip-substrate connection. USP2008107442582.
  16. Lim, Chee Chian; Hng, May Ting. Multi-chip electronic package with reduced stress. USP2013128604595.
  17. Lye,Poh Huat; Leong,Ak Wing. Optical integrated circuit package. USP2009017473889.
  18. Standing, Martin. Power semiconductor package. USP2015059041191.
  19. Yoshida, Hiroshi; Tojo, Tsuyoshi; Ozawa, Masafumi. Semiconductor device and package with high heat radiation effect. USP2004086777792.
  20. Hirokazu Honda JP. Semiconductor device having a flip chip cavity with lower stress and method for forming same. USP2002096445062.
  21. Hiroshi Yoshida JP; Tsuyoshi Tojo JP; Masafumi Ozawa JP. Semiconductor device package, and fabrication method thereof. USP2002116479889.
  22. Standing, Martin. Semiconductor package with conductive clip. USP2017109799623.
  23. Sims,Tyler. Solder seals within a switching system. USP2007067231112.
  24. Fukushima, Daisuke. Surface mounting package. USP2005126977339.
  25. Boon, Suan Jeung. Wafer level pre-packaged flip chip. USP2010107812447.
  26. Boon, Suan Jeung. Wafer level pre-packaged flip chip system. USP2010107808112.
  27. Boon, Suan Jeung. Wafer level pre-packaged flip chip systems. USP2010017646102.
  28. Wakana, Yoshinori; Kamoshida, Masaru; Igarashi, Takeshi; Kanno, Kiyotaka. Waterproof component-suppressing electronic control device. USP20190310238012.

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