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High performance data paths 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/00
  • G06F-013/00
출원번호 US-0093143 (1998-06-08)
발명자 / 주소
  • Krull Nicholas J.
  • Burns William A.
  • Selkirk Stephen S.
출원인 / 주소
  • Storage Technology Corporation
대리인 / 주소
    Brooks & Kushman P.C.
인용정보 피인용 횟수 : 167  인용 특허 : 20

초록

A system for busing data in a DASD controller is described. The system includes adapters serving computer elements such as processors and disk arrays. Cache memory in the controller is divided amongst memory cards. At least one switch is connected to each memory card. Bidirectional multichannel seri

대표청구항

[ What is claimed is:] [1.]1. A system for busing data in a direct access storage device (DASD) controller, the DASD controller serving a plurality of computer elements, the system comprising:a plurality of adapters, each adapter in communication with one of the computer elements;a plurality of memo

이 특허에 인용된 특허 (20)

  1. Davies David C. (Chelmsford MA) Vonada Donald G. (Stow MA), Clock recovery for serial data communications system.
  2. Mu Albert ; Larson Jeffrey D., Crossbar switch and method with reduced voltage swing and no internal blocking data path.
  3. Suemura Yoshihiko,JPX ; Henmi Naoya,JPX, Datalink system and communication network.
  4. Houlberg Christian L. (9524 Oneida St. Ventura CA 93004) Pacl Jeffrey J. (1024 E. Stroube St. Oxnard CA 93030), Digital interface circuit.
  5. Awiszio DesireA. (Worchester) Soman Satish (Hudson) Clark Paul H. (Westborough MA), Dual-path computer interconnect system with four-ported packet memory control.
  6. Ducaroir Francois ; Nakamura Karl S. ; Jenkins Michael O., Enhanced receiving chip for a computer monitor.
  7. Caspi Rami (Haifa ILX) Galin Robert (Cupertino CA), Flexible switching hub for a communication network.
  8. Levinson Frank H. (Palo Alto CA) Farley Mark J. (Napa CA) Vu Minh Q. (San Jose CA) Leung Calvin P.-K. (Newark CA), High speed network switch.
  9. Chen Dao-Long ; Waldron Robert D. ; Nguyen Khanh C., Integral bit error rate test system for serial data communication links.
  10. Iwatsuki Kazuko,JPX ; Wada Hiroyuki,JPX, LAN adaptor system for judging a port type from among a plurality of port types in accordance with a content of a contro.
  11. Ebersole Ronald J. (Beaverton OR) Pollack Frederick J. (Portland OR), Local area network with an active star topology comprising ring controllers having ring monitor logic function.
  12. Murray David E. ; Wooten David R., Low speed serial bus protocol and circuitry.
  13. Jain Vipin Kumar ; Nessett Danny M. ; Sherer William Paul, Method and apparatus for authentication process of a star or hub network connection ports by detecting interruption in link beat.
  14. Krause Jeffrey J. (Los Altos CA) Harris ; Jr. George W. (Mountain View CA) Lagueux ; Jr. Richard A. (San Jose CA) Kafiero Luca (Palo Alto CA) DeNicolo Maurilio T. (Mountain View CA) Mazzolo Mario (Ca, Method and apparatus for coupling computer work stations.
  15. Carusone ; Jr. Anthony (Tucson AZ) Garrigan Albert W. (Wappingers Falls NY) Hunsinger Wayne (Endwell NY) Moffitt Gerald T. (San Jose CA) Taylor Jordan M. (Poughkeepsie NY) Tendolkar Nandakamar N. (Wa, Method and apparatus for isolating faults in a network having serially connected links.
  16. Coleman John J. (Poughkeepsie NY) Coleman Ronald G. (Hyde Park NY) Monroe Owen K. (Port Ewen NY) Stucke Robert F. (Saugerties NY) Vanderbeck Elizabeth A. (Kingston NY) Bello Stephen E. (Kingston NY) , Multiprocessor system with distributed memory.
  17. McMillen Robert J. (Long Beach CA) Rosman Andrew (Los Alamitos CA), Packet switched multiport memory NXM switch node and processing method.
  18. Burzio Marco,ITX ; Pellegrino Paolo,ITX, Serializing-parallelizing circuit for high speed digital signals.
  19. Burns William ; Lucas Michael, System and method for multiplexing serial links.
  20. Haddock Stephen R. ; Harwood Michael J. ; Schneider Herb O., Use of video DRAM for memory storage in a local area network port of a switching hub.

이 특허를 인용한 특허 (167)

  1. Larson, Douglas A.; Cronin, Jeffrey J, Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system.
  2. Larson, Douglas A.; Cronin, Jeffrey J., Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system.
  3. Larson, Douglas A.; Cronin, Jeffrey J., Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system.
  4. Larson, Douglas A.; Cronin, Jeffrey J., Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system.
  5. Jeddeloh, Joseph M., Apparatus and method for direct memory access in a hub-based memory system.
  6. Jeddeloh,Joseph M., Apparatus and method for direct memory access in a hub-based memory system.
  7. Jeddeloh,Joseph M., Apparatus and method for direct memory access in a hub-based memory system.
  8. Radke,William; Peterson,James R., Apparatus and method for distributed memory control in a graphics processing system.
  9. Meyer, James W.; Kanski, Cory, Arbitration system and method for memory responses in a hub-based memory system.
  10. Meyer,James W.; Kanski,Cory, Arbitration system and method for memory responses in a hub-based memory system.
  11. Jeddeloh, Joseph, Buffer control system and method for a memory system having outstanding read and write request buffers.
  12. Jeddeloh, Joseph M., Buffer control system and method for a memory system having outstanding read and write request buffers.
  13. Jeddeloh,Joseph M., Buffer control system and method for a memory system having outstanding read and write request buffers.
  14. Chu, William W. Y., Computer system including CPU or peripheral bridge directly connected to a low voltage differential signal channel that communicates serial bits of a peripheral component interconnect bus transaction in opposite directions.
  15. Chu, William W. Y., Computer system including CPU or peripheral bridge directly connected to a low voltage differential signal channel that communicates serial bits of a peripheral component interconnect bus transaction in opposite directions.
  16. Chu, William W. Y., Computer system including CPU or peripheral bridge directly connected to a low voltage differential signal channel that communicates serial bits of a peripheral component interconnect bus transaction in opposite directions.
  17. Chu, William W. Y., Computer system including CPU or peripheral bridge to communicate serial bits of peripheral component interconnect bus transaction and low voltage differential signal channel to convey the serial bits.
  18. Chu, William W. Y., Computer system including CPU or peripheral bridge to communicate serial bits of peripheral component interconnect bus transaction and low voltage differential signal channel to convey the serial bits.
  19. Chu, William W. Y., Computer system including peripheral bridge to communicate serial bits of peripheral component interconnect bus transaction and low voltage differential signal channel to convey the serial bits.
  20. Chu, William W. Y., Data security method and device for computer modules.
  21. Chu, William W. Y., Data security method and device for computer modules.
  22. Chu, William W. Y., Data security method and device for computer modules.
  23. Chu, William W. Y., Data security method and device for computer modules.
  24. Chu, William W. Y., Data security method and device for computer modules.
  25. Chu, William W. Y., Data security method and device for computer modules.
  26. Chu, William W. Y., Data security method and device for computer modules.
  27. Chu, William W. Y., Data security method and device for computer modules.
  28. Porat,Ofer; Campbell,Brian K.; Xu,Jane; Bruno,Eric J.; Wilson,Paul C., Data storage system.
  29. LaBerge, Paul A., Delay line synchronizer apparatus and method.
  30. LaBerge, Paul A., Delay line synchronizer apparatus and method.
  31. LaBerge, Paul A., Delay line synchronizer apparatus and method.
  32. Bruner, Curtis H.; Carlson, Lance R.; Mast, Jeffrey E., Digital device configuration and method.
  33. Bruner, Curtis H.; Fletcher, John F.; Fletcher, Frida E. R., Digital device configuration and method.
  34. Bruner, Curtis H.; Fletcher, John F.; Fletcher, Frida E. R., Digital device configuration and method.
  35. Bruner, Curtis H.; Fletcher, John F.; Fletcher, Frida E. R., Digital device configuration and method.
  36. Bruner, Curtis H.; Fletcher, John F.; Fletcher, Frida E. R., Digital device configuration and method.
  37. Bruner, Curtis H.; Fletcher, John F.; Fletcher, Frida E. R., Digital device configuration and method.
  38. Bruner, Curtis H.; Fletcher, John F.; Fletcher, Frida E. R., Digital device configuration and method.
  39. Bruner, Curtis H.; Fletcher, John F.; Fletcher, Frida E. R., Digital device configuration and method.
  40. Bruner, Curtis H.; Fletcher, John F.; Fletcher, Frida E. R., Digital device configuration and method.
  41. LaBerge, Paul A., Dynamic command and/or address mirroring system and method for memory modules.
  42. LaBerge,Paul A., Dynamic command and/or address mirroring system and method for memory modules.
  43. Fenner, Martin, Enhanced computer processor and memory management architecture.
  44. Chengson, David P.; Wu, Chang-Hong, Low latency serial memory interface.
  45. Jeddeloh, Joseph M.; James, Ralph, Memory arbitration system and method having an arbitration packet protocol.
  46. Jeddeloh, Joseph M.; James, Ralph, Memory arbitration system and method having an arbitration packet protocol.
  47. Jeddeloh,Joseph M.; James,Ralph, Memory arbitration system and method having an arbitration packet protocol.
  48. Jeddeloh,Joseph M.; James,Ralph, Memory arbitration system and method having an arbitration packet protocol.
  49. Jeddeloh, Joseph M., Memory hub and access method having a sequencer and internal row caching.
  50. Lee, Terry R.; Jeddeloh, Joseph, Memory hub and access method having internal prefetch buffers.
  51. Lee,Terry R.; Jeddeloh,Joseph, Memory hub and access method having internal prefetch buffers.
  52. Lee,Terry R.; Jeddeloh,Joseph M., Memory hub and access method having internal prefetch buffers.
  53. Jeddeloh, Joseph M., Memory hub and method for memory sequencing.
  54. Jeddeloh,Joseph M., Memory hub and method for memory sequencing.
  55. Jeddeloh,Joseph M., Memory hub and method for memory sequencing.
  56. Jeddeloh, Joseph M., Memory hub and method for memory system performance monitoring.
  57. Jeddeloh,Joseph M., Memory hub and method for memory system performance monitoring.
  58. Jeddeloh,Joseph M., Memory hub and method for memory system performance monitoring.
  59. Jeddeloh,Joseph M., Memory hub and method for providing memory sequencing hints.
  60. Jeddeloh,Joseph M., Memory hub and method for providing memory sequencing hints.
  61. Jobs, Jeffrey R.; Stenglein, Thomas A., Memory hub architecture having programmable lane widths.
  62. Jobs, Jeffrey R.; Stenglein, Thomas A., Memory hub architecture having programmable lane widths.
  63. Jobs, Jeffrey R.; Stenglein, Thomas A., Memory hub architecture having programmable lane widths.
  64. Jobs, Jeffrey R.; Stenglein, Thomas A., Memory hub architecture having programmable lane widths.
  65. Jobs,Jeffrey R.; Stenglein,Thomas A., Memory hub architecture having programmable lane widths.
  66. Jeddeloh, Joseph M., Memory hub bypass circuit and method.
  67. Jeddeloh,Joseph M., Memory hub bypass circuit and method.
  68. Jeddeloh,Joseph M., Memory hub bypass circuit and method.
  69. Jeddeloh,Joseph M., Memory hub bypass circuit and method.
  70. Jeddeloh, Joseph M., Memory hub tester interface and method for use thereof.
  71. Jeddeloh,Joseph M., Memory hub tester interface and method for use thereof.
  72. Schnepper, Randy L., Memory hub with integrated non-volatile memory.
  73. Schnepper, Randy L., Memory hub with integrated non-volatile memory.
  74. Schnepper,Randy L., Memory hub with integrated non-volatile memory.
  75. Schnepper,Randy L., Memory hub with integrated non-volatile memory.
  76. Jeddeloh, Joseph M., Memory hub with internal cache and/or memory access prediction.
  77. Jeddeloh, Joseph M., Memory hub with internal cache and/or memory access prediction.
  78. Jeddeloh, Joseph M., Memory hub with internal cache and/or memory access prediction.
  79. Jeddeloh,Joseph M., Memory hub with internal cache and/or memory access prediction.
  80. Pax, George E.; Greeff, Roy E., Memory module and method having improved signal routing topology.
  81. Pax, George E.; Greeff, Roy E., Memory module and method having improved signal routing topology.
  82. Pax, George E.; Greeff, Roy E., Memory module and method having improved signal routing topology.
  83. Pax,George E.; Greeff,Roy E., Memory module and method having improved signal routing topology.
  84. Pax,George E.; Greeff,Roy E., Memory module and method having improved signal routing topology.
  85. Pax,George E.; Greeff,Roy E., Memory module and method having improved signal routing topology.
  86. Jeddeloh, Joseph M.; Lee, Terry R., Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link interface, and method of posting write requests in memory modules.
  87. Yi, Cheng; Liao, Heng; Leung, Calvin, Method and apparatus for SAS open address frame processing in SAS expanders.
  88. Singh, Shanker, Method and apparatus for memory with embedded processor.
  89. James,Ralph, Method and system for capturing and bypassing memory transactions in a hub-based memory system.
  90. James,Ralph, Method and system for capturing and bypassing memory transactions in a hub-based memory system.
  91. Jeddeloh, Joseph M.; Lee, Terry R., Method and system for controlling memory accesses to memory modules having a memory hub architecture.
  92. Jeddeloh,Joseph M.; Lee,Terry R., Method and system for controlling memory accesses to memory modules having a memory hub architecture.
  93. Miller, Michael; Thiesfeld, Charles William, Method and system for data path verification.
  94. Thiesfeld, Charles William; Miller, Michael Howard, Method and system for data path verification.
  95. James, Ralph, Method and system for synchronizing communications links in a hub-based memory system.
  96. James,Ralph, Method and system for synchronizing communications links in a hub-based memory system.
  97. Cronin, Jeffrey J.; Larson, Douglas A., Method and system for terminating write commands in a hub-based memory system.
  98. Cronin,Jeffrey J.; Larson,Douglas A., Method and system for terminating write commands in a hub-based memory system.
  99. Chu, William W. Y., Method of improving peripheral component interface communications utilizing a low voltage differential signal channel.
  100. Chu, William W. Y., Multiple module computer system and method including differential signal channel comprising unidirectional serial bit channels to transmit encoded peripheral component interconnect bus transaction data.
  101. Jeddeloh, Joseph M., Multiple processor system and method including multiple memory hub modules.
  102. Jeddeloh, Joseph M., Multiple processor system and method including multiple memory hub modules.
  103. Jeddeloh, Joseph M., Multiple processor system and method including multiple memory hub modules.
  104. Jeddeloh, Joseph M., Multiple processor system and method including multiple memory hub modules.
  105. Jeddeloh,Joseph M., Multiple processor system and method including multiple memory hub modules.
  106. Jeddeloh,Joseph M., Multiple processor system and method including multiple memory hub modules.
  107. Ngai,Henry P., Optimized topographies for dynamic allocation of PCI express lanes using differential muxes to additional lanes to a host.
  108. Chu, William W. Y., Password protected modular computer method and device.
  109. Chu, William W. Y., Password protected modular computer method and device.
  110. Chu, William W. Y., Password protected modular computer method and device.
  111. Jeddeloh,Joseph M.; Lee,Terry R., Posted write buffers and methods of posting write requests in memory modules.
  112. Lee, Terry R.; Jeddeloh, Joseph M., Reconfigurable memory module and method.
  113. Lee, Terry R.; Jeddeloh, Joseph M., Reconfigurable memory module and method.
  114. Lee, Terry R.; Jeddeloh, Joseph M., Reconfigurable memory module and method.
  115. Lee,Terry R.; Jeddeloh,Joseph M., Reconfigurable memory module and method.
  116. Bayer, Nimrod; Peleg, Aviely, Shared memory system for a tightly-coupled multiprocessor.
  117. Binkert, Nathan; Jouppi, Norm; Schreiber, Robert; Ahn, Jung Ho; McLaren, Moray, Synchronous optical bus providing communication between computer system components.
  118. LaBerge, Paul A., System and method for an asynchronous data buffer having buffer write and read pointers.
  119. LaBerge, Paul A., System and method for an asynchronous data buffer having buffer write and read pointers.
  120. LaBerge, Paul A., System and method for an asynchronous data buffer having buffer write and read pointers.
  121. Jeddeloh,Joseph M., System and method for arbitration of memory responses in a hub-based memory system.
  122. James,Ralph, System and method for communicating the synchronization status of memory modules during initialization of the memory modules.
  123. James,Ralph, System and method for communicating the synchronization status of memory modules during initialization of the memory modules.
  124. Jeddeloh, Joseph M., System and method for memory hub-based expansion bus.
  125. Jeddeloh, Joseph M., System and method for memory hub-based expansion bus.
  126. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
  127. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
  128. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
  129. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
  130. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
  131. Murphy,Tim, System and method for multiple bit optical data transmission in memory systems.
  132. Murphy,Tim, System and method for multiple bit optical data transmission in memory systems.
  133. Jeddeloh, Joseph M., System and method for on-board diagnostics of memory modules.
  134. Jeddeloh,Joseph M., System and method for on-board diagnostics of memory modules.
  135. Jeddeloh,Joseph M., System and method for on-board diagnostics of memory modules.
  136. Jeddeloh, Joseph M., System and method for on-board timing margin testing of memory modules.
  137. Jeddeloh,Joseph M., System and method for on-board timing margin testing of memory modules.
  138. Taylor,George R., System and method for optically interconnecting memory devices.
  139. Taylor,George R., System and method for optically interconnecting memory devices.
  140. Taylor,George R., System and method for optically interconnecting memory devices.
  141. Taylor,George R., System and method for optically interconnecting memory devices.
  142. Janzen, Jeffery W., System and method for optimizing interconnections of components in a multichip memory module.
  143. Janzen, Jeffery W., System and method for optimizing interconnections of components in a multichip memory module.
  144. Janzen, Jeffery W., System and method for optimizing interconnections of components in a multichip memory module.
  145. Ryan, Kevin J., System and method for optimizing interconnections of memory devices in a multichip module.
  146. Ryan, Kevin J., System and method for optimizing interconnections of memory devices in a multichip module.
  147. Ryan, Kevin J., System and method for optimizing interconnections of memory devices in a multichip module.
  148. Jeddeloh, Joseph M.; LaBerge, Paul, System and method for read synchronization of memory modules.
  149. Jeddeloh, Joseph M.; LaBerge, Paul A., System and method for read synchronization of memory modules.
  150. Jeddeloh,Joseph M.; LaBerge,Paul, System and method for read synchronization of memory modules.
  151. Jeddeloh,Joseph M.; LaBerge,Paul, System and method for read synchronization of memory modules.
  152. Jeddeloh,Joseph M.; Lee,Terry, System and method for selective memory module power management.
  153. Jeddeloh,Joseph M.; Lee,Terry, System and method for selective memory module power management.
  154. Jeddeloh,Joseph M.; Lee,Terry, System and method for selective memory module power management.
  155. Jeddeloh, Joseph M., System and method for self-testing and repair of memory modules.
  156. James, Ralph; Jeddeloh, Joe, System and method for transmitting data packets in a computer system having a memory hub architecture.
  157. James, Ralph; Jeddeloh, Joe, System and method for transmitting data packets in a computer system having a memory hub architecture.
  158. James,Ralph; Jeddeloh,Joe, System and method for transmitting data packets in a computer system having a memory hub architecture.
  159. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
  160. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
  161. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
  162. Jeddeloh, Joseph M.; Lee, Terry R., System for controlling memory accesses to memory modules having a memory hub architecture.
  163. Hannuksela, Miska, Video coding.
  164. Hannuksela, Miska, Video coding.
  165. Hannuksela,Miska, Video coding.
  166. Lee,Terry R.; Jeddeloh,Joseph M., Wavelength division multiplexed memory module, memory system and method.
  167. Lee,Terry R.; Jeddeloh,Joseph M., Wavelength division multiplexed memory module, memory system and method.
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