초록 ▼

An instruction scheduler in an optimizing compiler schedules instructions in a computer program by determining the lifetimes of fixed registers in the computer program. By determining the lifetimes of fixed registers, the instruction scheduler can achieve a schedule that has a higher degree of paral

An instruction scheduler in an optimizing compiler schedules instructions in a computer program by determining the lifetimes of fixed registers in the computer program. By determining the lifetimes of fixed registers, the instruction scheduler can achieve a schedule that has a higher degree of parallelism by relaxing dependences between instructions in independent lifetimes of a fixed register so that instructions can be scheduled earlier than would otherwise be possible if those dependences were precisely honored.

대표청구항 ▼

[ We claim:] [1.]1. An apparatus comprising:at least one processor that includes at least one fixed register;a memory coupled to the at least one processor;a computer program residing in the memory that includes a selected instruction that defines at least one fixed register; andan instruction sched

[ We claim:] [1.]1. An apparatus comprising:at least one processor that includes at least one fixed register;a memory coupled to the at least one processor;a computer program residing in the memory that includes a selected instruction that defines at least one fixed register; andan instruction scheduler residing in the memory and executed by the at least one processor, the instruction scheduler scheduling the selected instruction in a scheduling window, determining the lifetime in the scheduling window of the at least one fixed register defined in the selected instruction, and scheduling at least one other instruction within the lifetime of the at least one fixed register before scheduling any instruction that is in a different lifetime of the fixed register in the scheduling window.