초록 ▼

The present disclosure discloses an apparatus for generating a shaped waveform derived from a binary input signal. The apparatus receives a binary input signal and a sample clock signal. The sample clock signal changes the state of an up/down counter. The binary input signal controls the counting di

The present disclosure discloses an apparatus for generating a shaped waveform derived from a binary input signal. The apparatus receives a binary input signal and a sample clock signal. The sample clock signal changes the state of an up/down counter. The binary input signal controls the counting direction of the counter. The counter addresses a lookup table containing stored values. Also disclosed is the apparatus in which the lookup table output is converted to an analog signal by a digital-to-analog converter. The lookup table can be programmed such that the circuit output is equivalent to a filtered version of the binary input signal. The apparatus may optionally be enabled or disabled, such that the apparatus output assumes a predetermined state when disabled.

대표청구항 ▼

[ What is claimed is:] [1.]1. An apparatus for generating a shaped waveform derived from a binary input signal, comprising:a binary input signal;a sample clock signal;a counter circuit which outputs a state and is capable of incrementing or decrementing its state throughout a predetermined range of

[ What is claimed is:] [1.]1. An apparatus for generating a shaped waveform derived from a binary input signal, comprising:a binary input signal;a sample clock signal;a counter circuit which outputs a state and is capable of incrementing or decrementing its state throughout a predetermined range of minimum and maximum values, and which counter circuit further contains a direction input electrically connected to the binary input signal, and a count input electrically connected to the sample clock signal, such that the state of the counter increases each time the counter is triggered by the sample clock signal when the direction input is in a first state, and such that the state of the counter decreases each time the counter is triggered by the sample clock signal when the direction input is in a second state different from the first state, except when the counter is in its minimum state and the direction input indicates downward counting, in which case the counter remains in its minimum state, or when the counter is in its maximum state and the direction input indicates upward counting, in which case the counter remains in its maximum state;a lookup table, which stores addressable predetermined data values and includes an address input responsive to the counter circuit output, whereby the lookup table circuit outputs a predetermined data value associated with the address input value.