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Enhanced interconnection to ceramic substrates 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0376599 (1999-08-18)
발명자 / 주소
  • Pasco Robert W.
  • Reddy Srinivasa S. N.
  • Vallabhaneni Rao V.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Wood, Phillips, VanSanten, Clark & Mortimer
인용정보 피인용 횟수 : 44  인용 특허 : 16

초록

A semiconductor chip interposer increases fatigue life of interconnections between a first component having a relatively high thermal coefficient of expansion (TCE) and a second component having a relatively low TCE. The semiconductor chip interposer includes a thin metal plate having a plurality of

대표청구항

[ We claim:] [1.]1. A semiconductor chip interposer for increasing fatigue life of interconnections between a first component having a relatively high thermal coefficient of expansion (TCE) and a second component having a relatively low TCE, comprising:a thin substrate having a TCE intermediate the

이 특허에 인용된 특허 (16)

  1. Lee Michael Guang-Tzong ; Beilin Solomon I. ; Wang Wen-chou Vincent, Chip and board stress relief interposer.
  2. Coors William G. (Golden CO), Circuit board with coated metal support structure and method for making same.
  3. Nakatani Seiichi (Hirakata JPX) Hatakeyama Akihito (Suita JPX) Kawakita Kouji (Jouyou JPX) Sogou Hirishi (Nishinomiya JPX) Ogawa Tatsuo (Amagasaki JPX) Kojima Tamao (Suita JPX), Connecting member of a circuit substrate and method of manufacturing multilayer circuit substrates by using the same.
  4. Gaudenzi Gene J. (Purdy\s NY) Nihal Perwaiz (Hopewell Junction NY), Direct chip attach module (DCAM).
  5. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  6. Vafi Habib (San Diego CA) Beilin Solomon I. (San Carlos CA) Wang Wen-chou V. (Cupertino CA), Interconnect carriers having high-density vertical connectors and methods for making the same.
  7. Murakami Gen,JPX ; Mita Mamoru,JPX ; Kumakura Toyohiko,JPX ; Okabe Norio,JPX ; Komatsu Katsuji,JPX ; Shinzawa Shoji,JPX, Interposer for semiconductor device.
  8. Geldermans Pieter (Poughkeepsie NY) Mathad Gangadhara S. (Poughkeepsie NY), Method of fabricating a chip interposer.
  9. Mack Alfred (Poughkeepsie NY) McAllister Michael F. (Clintondale NY), Method of making a hybrid dielectric probe interposer.
  10. Ito Jun-ichi (Tokuyama JPX) Shimamoto Toshitsugu (Fujisawa JPX), Multilayer board and fabrication method thereof.
  11. Booth Richard B. (Wappingers Falls NY) Gephard Robert H. (Poughkeepsie NY) Gremban Bradley S. (Lake Katrine NY) Poetzinger Janet E. (Rochester MN) Shen David T. (Poughkeepsie NY), Parallel process interposer (PPI).
  12. Rostoker Michael D. (San Jose CA) Pasch Nicholas F. (Pacifica CA), Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interpos.
  13. Chance Dudley A. (Newton CT) Davidson Evan E. (Hopewell Junction NY) Dinger Timothy R. (Croton-on-Hudson NY) Goland David B. (Bedford Hills NY) Lapotin David P. (Carmel NY), Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance.
  14. Christie Frederick Richard (Endicott NY) Papathomas Kostas I. (Endicott NY) Wang David Wei (Vestal NY), Solder interconnection structure and process for making.
  15. Young Peter L. (Mercer Island WA), Thin film semiconductor interconnect module.
  16. Arldt Roy L. (Georgetown TX) Boyko Christina M. (Conklin NY) Cayson Burtran J. (Austin TX) Kozlowski Richard M. (Apalachin NY) Kulesza Joseph D. (Binghamton NY) Lauffer John M. (Waverly NY) Liu Phili, Via fill compositions for direct attach of devices and methods for applying same.

이 특허를 인용한 특허 (44)

  1. Dupuis, Timothy J.; Welland, David R.; Paul, Susanne A.; Niknejad, Ali M., Absolute power detector.
  2. Cooney, Robert C.; Wilkinson, Joseph M., Circuit board with an attached die and intermediate interposer.
  3. Hoang, Lan H.; Wu, Paul Ying-Fung, Composite flip-chip package with encased components and method of fabricating same.
  4. Hoang,Lan H.; Wu,Paul Ying Fung, Composite flip-chip package with encased components and method of fabricating same.
  5. Ishikawa, Koji, Connector and manufacturing method thereof.
  6. Shah, Sharad M.; Bach, David R.; Villani, Angelo; Palmer, Nicholas, Dual interposer packaging for high density interconnect.
  7. Meyer Berg,Georg; Vasquez,Barbara, Electronic component having at least one semiconductor chip and flip-chip contacts, and method for producing the same.
  8. Sterrett, Terry L.; Natekar, Devendra, Etched interposer for integrated circuit devices.
  9. Bocock, Ryan M.; Dupuis, Timothy J., Fast settling power amplifier regulator.
  10. Bocock,Ryan M.; Dupuis,Timothy J., Fast settling power amplifier regulator.
  11. Roy, Apurba, I-channel surface-mount connector with extended flanges.
  12. Nickerson, Robert M.; Spreitzer, Ronald L.; Conner, John C.; Taggart, Brian, Integrated circuit device mounting with folded substrate and interposer.
  13. Kline, Jerry D., Interposer for improved handling of semiconductor wafers and method of use of same.
  14. Kline, Jerry D., Matched set of integrated circuit chips selected from a multi wafer-interposer.
  15. Wu, Paul Ying Fung; Chee, Soon Shin, Method and apparatus for a power distribution system.
  16. Dupuis, Timothy J.; Bocock, Ryan M., Method and apparatus for controlling the output power of a power amplifier.
  17. Dupuis,Timothy J.; Bocock,Ryan M., Method and apparatus for controlling the output power of a power amplifier.
  18. Dupuis, Timothy J., Method and apparatus for protecting devices in an RF power amplifier.
  19. Dupuis,Timothy J., Method and apparatus for protecting devices in an RF power amplifier.
  20. John L. Pierce, Method for constructing a wafer interposer by using conductive columns.
  21. Kline, Jerry D., Method for constructing a wafer-interposer assembly.
  22. Kline, Jerry D., Method for manufacturing a wafer-interposer assembly.
  23. Pierce,John L., Method for producing a wafer interposer for use in a wafer interposer assembly.
  24. Kline, Jerry D., Method for selecting components for a matched set from a wafer-interposer assembly.
  25. Cooney, Robert C.; Wilkinson, Joseph M., Method of attaching die to circuit board with an intermediate interposer.
  26. Okamoto, Shinji; Takeuchi, Katsumi; Nomura, Yutaka, Method of manufacturing a connector chip.
  27. Wang,Sung Fei, Multi-chips stacked package.
  28. Ichikawa,Kinya, Patch substrate for external connection.
  29. Paul, Susanne A.; Dupuis, Timothy J., Power amplifier circuitry and method.
  30. Paul, Susanne A.; Dupuis, Timothy J., Power amplifier circuitry and method.
  31. Paul, Susanne A.; Dupuis, Timothy J., Power amplifier circuitry and method using an inductance coupled to power amplifier switching devices.
  32. Paul, Susanne A.; Dupuis, Timothy J., RF power amplifier and method for packaging the same.
  33. Paul,Susanne A.; Dupuis,Timothy J.; Pavelka,John Blake, RF power amplifier and method for packaging the same.
  34. Dupuis, Timothy J.; Welland, David R.; Niknejad, Ali M.; Paul, Susanne A., RF power detector.
  35. Dupuis, Timothy J.; Welland, David R.; Niknejad, Ali M.; Paul, Susanne A., RF power detector.
  36. Wang, Ge, Robust mezzanine BGA connector.
  37. Bernhard Reul DE, Solderable electrical connection element with a solder deposit.
  38. Ichikawa,Kinya, Substrate connector for integrated circuit devices.
  39. Brusso, Patricia A; Modi, Mitul B; McCormick, Carolyn R.; Cadena, Ruben; Subramanian, Sankara J; Martin, Edward L., Underfill device and method.
  40. Brusso, Patricia A; Modi, Mitul B; McCormick, Carolyn R.; Cadena, Ruben; Subramanian, Sankara J; Martin, Edward L., Underfill device and method.
  41. Pierce, John L., Wafer interposer assembly.
  42. Kline, Jerry D., Wafer level interposer.
  43. Kline, Jerry D., Wafer-interposer assembly.
  44. Pierce, John L., Wafer-interposer using a ceramic substrate.
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