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Invocation architecture for generally concurrent process resolution 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/16
출원번호 US-0339909 (1999-06-25)
발명자 / 주소
  • Fant Karl M.
출원인 / 주소
  • Theseus Research, Inc.
대리인 / 주소
    Steptoe & Johnson LLP
인용정보 피인용 횟수 : 38  인용 특허 : 15

초록

An invocation architecture for generally concurrent process resolution comprises a plurality of interconnected processors, some of the processors being homogeneous processors and others of the processors being special purpose processors. Each homogeneous processor being capable of invoking a connect

대표청구항

[ What is claimed is:] [1.]1. An invocation architecture for generally concurrent process resolution, comprising:a plurality of interconnected processors, some of the plurality of interconnected processors being a homogenous processor;each of the homogeneous processors being capable of creating an i

이 특허에 인용된 특허 (15)

  1. Helenius Allan (Westford MA) Lackey ; Jr. Stanley A. (Chelmsford MA) Northrup Thomas A. (Westford MA), Accelerator processor for a data processing system.
  2. Gilbreath ; Cecil R. ; Womble ; Jimmie L., Advanced array transform processor with fixed/floating point formats.
  3. Kalantery Nasser,GBX, Apparatus and method for parallel computation.
  4. Wheat Stephen R. (Albuquerque NM), Dynamic load balancing of applications.
  5. Fant Karl M., Invocation architecture for generally concurrent process resolution.
  6. Minemura Harumi (Kanagawa JPX) Nakamura Shunichiro (Kanagawa JPX), Join processor for a relational database, using multiple auxiliary processors.
  7. Hartung Michael H. (Tucson AZ) Nolta Arthur H. (Tucson AZ) Reed David G. (Tucson AZ) Tayler Gerald E. (Tucson AZ), Load balancing in a multiunit system.
  8. Eguchi Hiroyoshi (Hadano JPX) Yamada Norio (Hadano JPX) Kusuyama Itaru (Hadano JPX) Saitou Chikara (Hadano JPX), Method and apparatus for controlling job transfer between computer systems.
  9. DeBruler, Dennis L., Method and apparatus for handling interprocessor calls in a multiprocessor system.
  10. Schoen Eric J. (Austin TX), Method for load balancing seismic migration processing on a multiproccessor computer.
  11. Schweizer Anton,DEX, Method for operating a machine tool.
  12. Chastain David M. (Plano TX) Mankovich James E. (Colorado Springs CO) Gostin Gary B. (Coppell TX), Multi-processor computer system having self-allocating processors.
  13. Eadline Douglas J. (Bethlehem PA), Run-time system having nodes for identifying parallel tasks in a logic program and searching for available nodes to exec.
  14. Furtek Frederick C. (Arlington MA), System for programming graphically a programmable, asynchronous logic cell and array.
  15. Wang Yulun (Goleta CA) Srinivasan Partha (Goleta CA), Three-dimensional vector co-processor having I, J, and K register files and I, J, and K execution units.

이 특허를 인용한 특허 (38)

  1. Hoffberg, Steven M.; Hoffberg-Borghesani, Linda I., Adaptive pattern recognition based controller apparatus and method and human-interface therefore.
  2. Hoffberg, Steven M.; Hoffberg-Borghesani, Linda I., Alarm system controller and a method for controlling an alarm system.
  3. Gelvin, David C.; Girod, Lewis D.; Kaiser, William J.; Merrill, William M.; Newberg, Frederic; Pottie, Gregory J.; Sipos, Anton I.; Vardhan, Sandeep, Apparatus for compact internetworked wireless integrated network sensors (WINS).
  4. Gelvin, David C.; Girod, Lewis D.; Kaiser, William J.; Merrill, William M.; Newberg, Fredric; Pottie, Gregory J.; Sipos, Anton I.; Vardhan, Sandeep, Apparatus for compact internetworked wireless integrated network sensors (WINS).
  5. Gelvin, David C.; Girod, Lewis D.; Kaiser, William J.; Merrill, William M.; Newberg, Fredric; Pottie, Gregory J.; Sipos, Anton I.; Vardhan, Sandeep, Apparatus for internetworked hybrid wireless integrated network sensors (WINS).
  6. Gelvin, David C.; Girod, Lewis D.; Kaiser, William J.; Merrill, William M.; Newberg, Fredric; Pottie, Gregory J.; Sipos, Anton I.; Vardhan, Sandeep, Apparatus for internetworked wireless integrated network sensors (WINS).
  7. Gelvin, David C.; Girod, Lewis D.; Kaiser, William J.; Newberg, Fredric; Pottie, Gregory J.; Sipos, Anton I.; Vardhan, Sandeep; Merrill, William M., Apparatus for internetworked wireless integrated network sensors (WINS).
  8. Gelvin, David C.; Girod, Lewis D.; Kaiser, William J.; Newberg, Fredric; Pottie, Gregory J.; Sipos, Anton I.; Vardhan, Sandeep; Merrill, William M., Apparatus for internetworked wireless integrated network sensors (WINS).
  9. Eggers,Susan Jane; Mercaldi,Martha Allen; Michelson,Kenneth Alan; Oskin,Mark Henry; Petersen,Andrew Kinoshita; Putnam,Andrew Richard; Schwerin,Andrew Michalski; Swanson,Steven James, Building a wavecache.
  10. Klots, Boris; Bamford, Roger, Communication architecture for distributed computing environment.
  11. Melton, Benjamin Wiley; Johnson, Stephen Curtis, Compact logic evaluation gates using null convention.
  12. Rutten, Hubert J. M.; van Ruyssevelt, Frank; Wilkinson, David, Document producing support system.
  13. Erstad,David O.; Carlson,Roy M., Error recovery in asynchronous combinational logic circuits.
  14. Buck, Ian A.; Aarts, Bastiaan, Expressing parallel execution relationships in a sequential programming language.
  15. Kaler, Christopher G.; Kruv, Steven J., Generic application server and method of operation therefor.
  16. Kaler,Christopher G.; Kruy,Steven J., Generic application server and method of operation therefor.
  17. Johnston, Scott E; Fant, Karl Michael, Hum generation circuitry.
  18. Singh, Gajendra Prasad; Desai, Shaishav, Hum generation using representative circuitry.
  19. Singh, Gajendra Prasad, Implementation method for fast NCL data path.
  20. Hoffberg, Steven M.; Hoffberg-Borghesani, Linda I., Internet appliance system and method.
  21. Gelvin, David C.; Girod, Lewis D.; Kaiser, William J.; Merrill, William M.; Newberg, Fredric; Pottie, Gregory J.; Sipos, Anton I.; Vardhan, Sandeep, Method and apparatus for distributed signal processing among internetworked wireless integrated network sensors (WINS).
  22. Gelvin, David C.; Girod, Lewis D.; Kaiser, William J.; Merrill, William M.; Newberg, Fredric; Pottie, Gregory J.; Sipos, Anton I.; Vardhan, Sandeep, Method and apparatus for internetworked wireless integrated network sensor (WINS) nodes.
  23. Fant, Karl M., Method and language for process expression.
  24. Gelvin, David C.; Girod, Lewis D.; Kaiser, William J.; Merrill, William M.; Newberg, Frederic; Pottie, Gregory J.; Sipos, Anton I.; Vardhan, Sandeep, Method for internetworked hybrid wireless integrated network sensors (WINS).
  25. Gelvin, David C.; Girod, Lewis D.; Kaiser, William J.; Merrill, William M.; Newberg, Fredric; Pottie, Gregory J.; Sipos, Anton I.; Vardhan, Sandeep, Method for internetworked hybrid wireless integrated network sensors (WINS).
  26. Gelvin, David C.; Girod, Lewis D.; Kaiser, William J.; Newberg, Fredric; Pottie, Gregory J., Method for vehicle internetworks.
  27. Gelvin, David C.; Girod, Lewis D.; Kaiser, William J.; Newberg, Fredric; Pottie, Gregory J., Method for vehicle internetworks.
  28. Patkar, Niteen; Alasti, Ali; Van Dyke, Don; Van Dyke, Korbin; Thusoo, Shalesh; Purcell, Stephen C.; Malalur, Govind, Method of manufacture and apparatus of an integrated computing system.
  29. Singh, Gajendra Prasad, Multi-threshold flash NCL circuitry.
  30. Singh, Gajendra Prasad, Multi-threshold flash NCL logic circuitry with flash reset.
  31. Krieger, Orran Y.; Sinharoy, Balaram; Tremaine, Robert B.; Wisniewski, Robert W., Prefetch engine based translation prefetching.
  32. Buskens, Richard W.; Liim, Tim T.; Lin, Yow Jian; Mishra, Sunil K.; Siddiqui, Muhammad A.; Suchaczewski, Timothy A., Selecting a processor to run an executable of a distributed software application upon startup of the distributed software application.
  33. Singh, Gajendra Prasad; Terrill, Richard Shaw, Self-ready flash null convention logic.
  34. Carlson, Roy M.; Erstad, David O., Single event hardening of null convention logic circuits.
  35. Carlson, Roy M.; Erstad, David O., System level hardening of asynchronous combinational logic.
  36. Fant, Karl, Systems and methods using an invocation model of process expression.
  37. Oskin, Mark H.; Swanson, Steven J.; Eggers, Susan J., Wavescalar architecture having a wave order memory.
  38. Oskin, Mark H.; Swanson, Steven J.; Eggers, Susan J., Wavescalar architecture having a wave order memory.
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