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[미국특허] Interconnect and system for making temporary electrical connections to semiconductor components 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/02
  • G01R-031/26
출원번호 US-0916587 (1997-08-22)
발명자 / 주소
  • Farnworth Warren M.
  • Akram Salman
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Gratton
인용정보 피인용 횟수 : 24  인용 특허 : 62

초록 ▼

An interconnect and system for making temporary electrical connections with semiconductor components are provided. The interconnect can be included in a wafer level test system for testing semiconductor wafers, or in a die level test system for testing singulated dice and chip scale packages. The in

대표청구항 ▼

[ What is claimed is:] [1.]1. An interconnect for testing a semiconductor component having a plurality of contacts comprising:a substrate;a plurality of conductors on the substrate configured for electrical communication with external circuitry;a plurality of pads on the substrate in electrical comm

이 특허에 인용된 특허 (62) 인용/피인용 타임라인 분석

  1. Jiang Tongbi ; Wu Zhiqiang ; Kao David ; Yang Rongsheng, Anisotropic conductive interconnect material for electronic devices, method of use and resulting product.
    상세보기
  2. Farnworth Warren M. ; Akram Salman ; Wood Alan G. ; Hembree David R. ; Wark James M. ; Jacobson John O., Apparatus for testing semiconductor wafers.
    상세보기
  3. Farnworth Warren M. ; Akram Salman ; Wood Alan G. ; Hembree David R. ; Wark James M. ; Jacobson John O., Apparatus for testing semiconductor wafers.
    상세보기
  4. Hembree David R. ; Farnworth Warren M. ; Wood Alan G. ; Gochnour Derek ; Akram Salman, Carrier and system for testing bumped semiconductor components.
    상세보기
  5. Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID) Hembree David R. (Boise ID), Carrier for testing an unpackaged semiconductor die.
    상세보기
  6. Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID), Carrier having interchangeable substrate used for testing of semiconductor dies.
    상세보기
  7. Wood Alan G. ; Farnworth Warren M., Carrier having interchangeable substrate used for testing of semiconductor dies.
    상세보기
  8. Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Brooks Mike (Caldwell ID), Carrier having slide connectors for testing unpackaged semiconductor dice.
    상세보기
  9. Wood Alan G. (Boise ID) Hembree David R. (Boise ID) Farnworth Warren M. (Nampa ID), Clamped carrier for testing of semiconductor dies.
    상세보기
  10. Farnworth Warren M. ; Akram Salman, Compliant contact system with alignment structure for testing unpackaged semiconductor device.
    상세보기
  11. Farnworth Warren M. ; Akram Salman ; Wood Alan G., Compliant interconnect for testing a semiconductor die.
    상세보기
  12. Scholz Kenneth D. (4150 Willmar Dr. Palo Alto CA 94306), Compressive bump-and-socket interconnection scheme for integrated circuits.
    상세보기
  13. Khandros Igor Y. ; Mathieu Gaetar L., Contact structure device for interconnections, interposer, semiconductor assembly and package using the same and method.
    상세보기
  14. Farnworth Warren M. ; Wood Alan G. ; Hembree David R. ; Akram Salman, Conventionally sized temporary package for testing semiconductor dice.
    상세보기
  15. Farnworth Warren M. ; Wood Alan G. ; Hembree David R. ; Akram Salman, Conventionally sized temporary package for testing semiconductor dice.
    상세보기
  16. Farnworth Warren M., Direct connect carrier for testing semiconductor dice and method of fabrication.
    상세보기
  17. Akram Salman ; Wark James M. ; Farnworth Warren M., Direct connect interconnect for testing semiconductor dice and wafers.
    상세보기
  18. Wood Alan G. ; Corbett Tim J. ; Chadwick Gary L. ; Huang Chender ; Kinsman Larry D., Discrete die burn-in for nonpackaged die.
    상세보기
  19. Wood Alan G. ; Corbett Tim J. ; Chadwick Gary L. ; Huang Chender ; Kinsman Larry D., Discrete die burn-in for nonpackaged die.
    상세보기
  20. Akram Salman (Boise ID) Farnworth Warren M. (Nampa ID) Wood Alan G. (Boise ID), Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads.
    상세보기
  21. Akram Salman ; Wood Alan G. ; Farnworth Warren M., High speed temporary package and interconnect for testing semiconductor dice and method of fabrication.
    상세보기
  22. Hembree David R. ; Akram Salman ; Farnworth Warren M. ; Wood Alan G. ; Wark James M. ; Gochnour Derek, Hybrid interconnect and system for testing semiconductor dice.
    상세보기
  23. Volz Keith L. (Jamestown NC) Renn Robert M. (Pfafftown NC) Irlbeck Robert D. (Greensboro NC) Deak Frederick R. (Kernersville NC), Integrated circuit chip testing apparatus.
    상세보기
  24. Hembree David R. ; Jacobson John O. ; Wark James M. ; Farnworth Warren M. ; Akram Salman ; Wood Alan G., Interconnect for making temporary electrical connections with bumped semiconductor components.
    상세보기
  25. Farnworth Warren M. ; Akram Salman, Interconnect for semiconductor components and method of fabrication.
    상세보기
  26. Farnworth Warren M. ; Gochnour Derek ; Akram Salman, Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with co.
    상세보기
  27. Farnworth Warren M. ; Gochnour Derek ; Akram Salman, Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps.
    상세보기
  28. Leedy Glenn J. (1061 E. Mountain Dr. Santa Barbara CA 93108), Making and testing an integrated circuit using high density probe points.
    상세보기
  29. Farnworth Warren (Nampa ID) Wood Alan (Boise ID), Method and apparatus for manufacturing known good semiconductor die.
    상세보기
  30. Hembree David R. ; Farnworth Warren M. ; Wood Alan G., Method and apparatus for testing an unpackaged semiconductor die.
    상세보기
  31. Farnworth Warren M. ; Akram Salman, Method for fabricating a multi chip module with alignment member.
    상세보기
  32. Farnworth Warren M. (Nampa ID), Method for fabricating a penetration limited contact having a rough textured surface.
    상세보기
  33. Akram Salman (Boise ID) Farnworth Warren M. (Nampa ID) Wood Alan G. (Boise ID), Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice.
    상세보기
  34. Akram Salman ; Farnworth Warren M. ; Wood Alan G., Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate.
    상세보기
  35. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Method for fabricating chip modules.
    상세보기
  36. Akram Salman ; Farnworth Warren M. ; Wood Alan G., Method for fabricating semiconductor components using focused laser beam.
    상세보기
  37. Hofmann Jim (Boise ID) Stansbury Darryl (Boise ID), Method for forming a screen for screen printing a pattern of small closely spaced features onto a substrate.
    상세보기
  38. Gochnour Derek (Boise ID) Farnworth Warren M. (Nampa ID), Method for forming an interconnect for testing unpackaged semiconductor dice.
    상세보기
  39. Gochnour Derek ; Farnworth Warren M., Method for forming an interconnect for testing unpackaged semiconductor dice.
    상세보기
  40. Tuttle Mark E., Method for surface mounting electrical components to a substrate.
    상세보기
  41. Akram Salman ; Hembree David R. ; Farnworth Warren M. ; Gochnour Derek ; Wood Alan G. ; Jacobson John O., Method for testing semiconductor components.
    상세보기
  42. Akram Salman ; Wood Alan G. ; Hembree David R. ; Farnworth Warren M., Method for testing semiconductor dice and chip scale packages.
    상세보기
  43. Farnworth Warren M. ; Wood Alan G. ; Hembree David R. ; Akram Salman, Method for testing semiconductor dice with conventionally sized temporary packages.
    상세보기
  44. Farnworth Warren M., Method for testing semiconductor packages using oxide penetrating test contacts.
    상세보기
  45. Leedy Glenn J. (1061 E. Mountain Dr. Santa Barbara CA 93108), Method of making a flexible tester surface for testing integrated circuits.
    상세보기
  46. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of making contact tip structures.
    상세보기
  47. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of planarizing tips of probe elements of a probe card assembly.
    상세보기
  48. Akram Salman ; Farnworth Warren M. ; Wood Alan G. ; Hembree David R., Method, apparatus and system for testing bumped semiconductor components.
    상세보기
  49. Akram Salman, Microbump interconnect for semiconductor dice.
    상세보기
  50. Farnworth Warren M. ; Akram Salman, Multi chip module including semiconductor wafer or dice, interconnect substrate, and alignment member.
    상세보기
  51. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Multi chip module with conductive adhesive layer.
    상세보기
  52. Akram Salman ; Farnworth Warren M., Non-oxidizing touch contact interconnect for semiconductor test systems and method of fabrication.
    상세보기
  53. Shimada Yuzo,JPX ; Senba Naoji,JPX ; Takahashi Nobuaki,JPX, Semiconductor device and method of fabricating the same.
    상세보기
  54. Akram Salman ; Hembree David R., Semiconductor interconnect having test structures for evaluating electrical characteristics of the interconnect.
    상세보기
  55. Farnworth Warren M. ; Wood Alan G. ; Brooks Mike, Semiconductor package including flex circuit, interconnects and dense array external contacts.
    상세보기
  56. Smith Kenneth R. (Plano TX), Singulated bare die tester and method of performing forced temperature electrical tests and burn-in.
    상세보기
  57. Wood Alan G. ; Doan Trung Tri ; Farnworth Warren M. ; Corbett Tim J., Substrate having self limiting contacts for establishing an electrical connection with a semiconductor die.
    상세보기
  58. Hembree David R. ; Jacobson John O. ; Wark James M. ; Farnworth Warren M. ; Akram Salman ; Wood Alan G., System and interconnect for making temporary electrical connections with bumped semiconductor components.
    상세보기
  59. Akram Salman ; Hembree David R. ; Farnworth Warren M. ; Gochnour Derek ; Wood Alan G. ; Jacobson John O., System for testing semiconductor components.
    상세보기
  60. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Temporary package, system, and method for testing semiconductor dice and chip scale packages.
    상세보기
  61. Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID) Hembree David R. (Boise ID), Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die.
    상세보기
  62. Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID) Hembree David R. (Boise ID), Z-axis interconnect for discrete die burn-in for nonpackaged die.
    상세보기

이 특허를 인용한 특허 (24) 인용/피인용 타임라인 분석

  1. Cram, Daniel P., Conductive polymer contact system and test method for semiconductor components.
    상세보기
  2. Farnworth,Warren M.; Akram,Salman, Contact for semiconductor components.
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  3. Sanders, David L., Contact probe with off-centered back-drilled aperture.
    상세보기
  4. Ben Jamaa, Haykel, Device for electrically testing the interconnections of a microelectronic device.
    상세보기
  5. Akram, Salman, Electrical contact.
    상세보기
  6. Hembree, David R.; Farnworth, Warren M.; Wark, James M., Force applying probe card and test system for semiconductor wafers.
    상세보기
  7. Farnworth, Warren M., Method and system for fabricating semiconductor components using wafer level contact printing.
    상세보기
  8. Farnworth, Warren M., Method for fabricating a semiconductor component using contact printing.
    상세보기
  9. Farnworth, Warren M.; Akram, Salman, Method for fabricating a test interconnect for bumped semiconductor components.
    상세보기
  10. Farnworth, Warren M.; Akram, Salman, Method for fabricating an interconnect for making temporary electrical connections to semiconductor components.
    상세보기
  11. James,Steven L.; Tandy, deceased,William D.; Tandy, legal representative,Lori, Method for fabricating semiconductor components using mold cavities having runners configured to minimize venting.
    상세보기
  12. Akram, Salman, Method of forming an electrical contact.
    상세보기
  13. Akram, Salman, Method of forming an electrical contact.
    상세보기
  14. Chang, Myung Whun; Lee, Dae Hyeong; Hong, Ki Pyo, Method of repairing a probe board.
    상세보기
  15. Chang, Myung Whun; Lee, Dae Hyeong; Hong, Ki Pyo, Method of repairing probe board and probe board using the same.
    상세보기
  16. James,Steven L.; Tandy, legal representative,Lori; Tandy, deceased,William D., Semiconductor component having dummy segments with trapped corner air.
    상세보기
  17. James, Steven L.; Tandy, legal representative, Lori, System for fabricating semiconductor components using mold cavities having runners configured to minimize venting.
    상세보기
  18. Warren M. Farnworth ; Salman Akram, Test interconnect for semiconductor components having bumped and planar contacts.
    상세보기
  19. Farnworth, Warren M.; Akram, Salman, Test interconnect having suspended contacts for bumped semiconductor components.
    상세보기
  20. Cram, Daniel P., Test method for electronic modules using contractors and conductive polymer contacts.
    상세보기
  21. Cram,Daniel P., Test method for semiconductor components using anisotropic conductive polymer contact system.
    상세보기
  22. Cram,Daniel P., Test method for semiconductor components using conductive polymer contact system.
    상세보기
  23. Cram, Daniel P., Test system for electronic modules having contactors with spring segment terminal portions.
    상세보기
  24. Akram, Salman, Test system for silicon substrate having electrical contacts.
    상세보기

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