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Millimeter wave semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/04
  • H01L-023/06
출원번호 US-0368430 (1999-08-05)
우선권정보 JPX, 19980807, 10-223848
발명자 / 주소
  • Kakimoto Noriko,JPX
  • Suematsu Eiji,JPX
출원인 / 주소
  • Sharp Kabushiki Kaisha, JPX
인용정보 피인용 횟수 : 43  인용 특허 : 6

초록 ▼

A millimeter wave semiconductor device is comprised of a millimeter wave device, a wiring substrate with the millimeter wave device mounted thereto, and a sealing cap with a conductor on a surface thereof for sealing the millimeter wave device. The sealing cap has a ground potential at the conductor

대표청구항 ▼

[ What is claimed is:] [1.]1. A millimeter wave semiconductor device comprising:a millimeter wave device;a wiring substrate with said millimeter wave device mounted thereto; anda sealing cap having a surface with a conductor thereon for sealing said millimeter wave device, wherein said sealing cap h

이 특허에 인용된 특허 (6)

  1. Schelhorn Robert L. (Vincentown NJ), Metallized ceramic circuit package.
    상세보기
  2. Williams Dylan F. (Boulder CO) Hayden Larry G. (Louisville CO), Method and apparatus for dampening resonant modes in packaged microwave circuits.
    상세보기
  3. Greenman Norman L. ; Hernandez Jorge M. ; Panicker M. P. Ramachandra, Method of making microwave circuit package.
    상세보기
  4. Chan Steven S. (Alhambra CA) Stones D. Ian (Torrance CA), Millimeter module package.
    상세보기
  5. Suematsu Eiji,JPX, Phase-locked oscillator for microwave/millimeter-wave ranges.
    상세보기
  6. Yamamura Shigeyuki (Sagamihara JPX), Semiconductor device mounted in a housing having an increased cutoff frequency.
    상세보기

이 특허를 인용한 특허 (43)

  1. Lee, Sang Ho; Ju, Jong Wook; Kwon, Hyeog Chan, Adhesive/spacer island structure for multiple die package.
    상세보기
  2. Lee, Sang Ho; Ju, Jong Wook; Kwon, Hyeog Chan; Karnezos, Marcos, Adhesive/spacer island structure for stacking over wire bonded die.
    상세보기
  3. Yu, Xuequan; Bai, Yadong; Yu, Ping, Chip package and packaging method.
    상세보기
  4. Kawabata, Kenichi; Hayakawa, Toshio; Okubo, Toshiro, Electronic circuit package.
    상세보기
  5. Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati; Chow, Seng Guan, Encapsulant cavity integrated circuit package system and method of fabrication thereof.
    상세보기
  6. Gremillet, Patrick; Ledain, Bernard, Hyperfrequency housing occupying a small surface area and mounting of such a housing on a circuit.
    상세보기
  7. Park, Soo-San; Kwon, Hyeog Chan; Lee, Sang-Ho; Ha, Jong-Woo, Integrated circuit package system including stacked die.
    상세보기
  8. Pendse, Rajendra D., Integrated circuit package system including zero fillet resin.
    상세보기
  9. Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati; Chow, Seng Guan, Integrated circuit package system with an encapsulant cavity and method of fabrication thereof.
    상세보기
  10. Chow, Seng Guan; Shim, II Kwon; Han, Byung Joon, Integrated circuit package system with exposed interconnects.
    상세보기
  11. Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati; Chow, Seng Guan, Integrated circuit packaging system with a component in an encapsulant cavity and method of fabrication thereof.
    상세보기
  12. Rofougaran, Ahmadreza, Method and system for communicating via flip-chip die and package waveguides.
    상세보기
  13. Karnezos,Marcos, Method for making a semiconductor multi-package module having wire bond interconnect between stacked packages.
    상세보기
  14. Karnezos, Marcos; Carson, Flynn; Kim, Youngcheol, Method for making semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package.
    상세보기
  15. Karnezos,Marcos, Method of fabricating a semiconductor assembly including chip scale package and second substrate with exposed substrate surfaces on upper and lower sides.
    상세보기
  16. Karnezos, Marcos, Method of fabricating a semiconductor multi package module having an inverted package stacked over ball grid array (BGA) package.
    상세보기
  17. Karnezos,Marcos, Method of fabricating a semiconductor multi-package module having a second package substrate with an exposed metal layer wire bonded to a first package substrate.
    상세보기
  18. Karnezos,Marcos, Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package.
    상세보기
  19. Karnezos, Marcos, Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages.
    상세보기
  20. Karnezos, Marcos, Method of fabricating a semiconductor multipackage module including a processor and memory package assemblies.
    상세보기
  21. Karnezos, Marcos, Method of fabricating module having stacked chip scale semiconductor packages.
    상세보기
  22. Karnezos,Marcos, Module having stacked chip scale semiconductor packages.
    상세보기
  23. Chow, Seng Guan; Kuan, Heap Hoe, Multi-chip package system.
    상세보기
  24. Karnezos, Marcos, Multiple chip package module having inverted package stacked over die.
    상세보기
  25. Karnezos, Marcos, Multiple chip package module including die stacked over encapsulated package.
    상세보기
  26. Mannak, Jan Hendrik; Maatman, Ivo Antoni Gerardus, Package for microwave components.
    상세보기
  27. Chen, Howard E.; Read, Matthew Sean; Nguyen, Hoang Mong; LoBianco, Anthony James; Zhang, Guohao; Hoang, Dinhphuoc Vu, Racetrack design in radio frequency shielding applications.
    상세보기
  28. Chen, Howard E.; Read, Matthew Sean; Nguyen, Hoang Mong; LoBianco, Anthony James; Zhang, Guohao; Hoang, Dinhphuoc Vu, Racetrack layout for radio frequency isolation structure.
    상세보기
  29. Chen, Howard E.; Read, Matthew Sean; Nguyen, Hoang Mong; LoBianco, Anthony James; Zhang, Guohao; Hoang, Dinhphuoc Vu, Racetrack layout for radio frequency shielding.
    상세보기
  30. Chen, Howard E.; Read, Matthew Sean; Nguyen, Hoang Mong; LoBianco, Anthony James; Zhang, Guohao; Hoang, Dinhphuoc Vu, Radio frequency isolation structure with racetrack.
    상세보기
  31. Karnezos,Marcos; Shim,IL Kwon; Han,Byung Joon; Ramakrishna,Kambhampati; Chow,Seng Guan, Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides.
    상세보기
  32. Karnezos,Marcos, Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages.
    상세보기
  33. Karnezos, Marcos, Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages.
    상세보기
  34. Karnezos,Marcos, Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages.
    상세보기
  35. Karnezos,Marcos, Semiconductor multi-package module having wire bond interconnect between stacked packages.
    상세보기
  36. Karnezos, Marcos, Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages.
    상세보기
  37. Karnezos, Marcos; Carson, Flynn; Kim, Youngcheol, Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package.
    상세보기
  38. Karnezos,Marcos; Carson,Flynn; Kim,Youngcheol, Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package.
    상세보기
  39. Karnezos,Marcos; Carson,Flynn, Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides.
    상세보기
  40. Karnezos,Marcos; Shim,Il Kwon; Han,Byung Joon; Ramakrishna,Kambhampati; Chow,Seng Guan, Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides.
    상세보기
  41. Carson, Flynn, Stacked integrated circuit package system and method of manufacture therefor.
    상세보기
  42. Kwon, Hyeog Chan; Karnezos, Marcos, Stacked semiconductor package having adhesive/spacer structure and insulation.
    상세보기
  43. Okubora, Akihiko, Three-dimensional integrated device.
    상세보기

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