$\require{mediawiki-texvc}$
  • 검색어에 아래의 연산자를 사용하시면 더 정확한 검색결과를 얻을 수 있습니다.
  • 검색연산자
검색도움말
검색연산자 기능 검색시 예
() 우선순위가 가장 높은 연산자 예1) (나노 (기계 | machine))
공백 두 개의 검색어(식)을 모두 포함하고 있는 문서 검색 예1) (나노 기계)
예2) 나노 장영실
| 두 개의 검색어(식) 중 하나 이상 포함하고 있는 문서 검색 예1) (줄기세포 | 면역)
예2) 줄기세포 | 장영실
! NOT 이후에 있는 검색어가 포함된 문서는 제외 예1) (황금 !백금)
예2) !image
* 검색어의 *란에 0개 이상의 임의의 문자가 포함된 문서 검색 예) semi*
"" 따옴표 내의 구문과 완전히 일치하는 문서만 검색 예) "Transform and Quantization"

통합검색

도움말도움말
상세검색 다국어 입력

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

특허 상세정보

MyON담기
내보내기 페이스북 공유 카카오톡 공유

Millimeter wave semiconductor device

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H01L-023/04    H01L-023/06   
미국특허분류(USC) 257/728 ; 257/678 ; 257/729 ; 257/730
출원번호 US-0368430 (1999-08-05)
우선권정보 JPX, 19980807, 10-223848
발명자 / 주소
  • Kakimoto Noriko,JPX
  • Suematsu Eiji,JPX
출원인 / 주소
  • Sharp Kabushiki Kaisha, JPX
인용정보 피인용 횟수 : 43  인용 특허 : 6
초록
▼

A millimeter wave semiconductor device is comprised of a millimeter wave device, a wiring substrate with the millimeter wave device mounted thereto, and a sealing cap with a conductor on a surface thereof for sealing the millimeter wave device. The sealing cap has a ground potential at the conductor provided on the surface thereof and the sealing cap has an internal surface spaced from an upper surface of the wiring substrate by less than one fourth of a spatial wavelength of a frequency applied. This can prevent creation of a waveguide mode in a sealed ...

대표
청구항
▼

[ What is claimed is:] [1.]1. A millimeter wave semiconductor device comprising:a millimeter wave device;a wiring substrate with said millimeter wave device mounted thereto; anda sealing cap having a surface with a conductor thereon for sealing said millimeter wave device, wherein said sealing cap has a ground potential at said conductor and is shaped so as to prevent creation of a waveguide mode in a sealed space for a frequency applied,wherein said sealing cap includes a meshed conductor having so fine meshes as to prevent an electromagnetic wave of an...

이 특허에 인용된 특허 (6)

  1. Schelhorn Robert L. (Vincentown NJ), Metallized ceramic circuit package.
  2. Williams Dylan F. (Boulder CO) Hayden Larry G. (Louisville CO), Method and apparatus for dampening resonant modes in packaged microwave circuits.
  3. Greenman Norman L. ; Hernandez Jorge M. ; Panicker M. P. Ramachandra, Method of making microwave circuit package.
  4. Chan Steven S. (Alhambra CA) Stones D. Ian (Torrance CA), Millimeter module package.
  5. Suematsu Eiji,JPX, Phase-locked oscillator for microwave/millimeter-wave ranges.
  6. Yamamura Shigeyuki (Sagamihara JPX), Semiconductor device mounted in a housing having an increased cutoff frequency.

이 특허를 인용한 특허 (43)

  1. Lee, Sang Ho; Ju, Jong Wook; Kwon, Hyeog Chan, Adhesive/spacer island structure for multiple die package.
  2. Lee, Sang Ho; Ju, Jong Wook; Kwon, Hyeog Chan; Karnezos, Marcos, Adhesive/spacer island structure for stacking over wire bonded die.
  3. Yu, Xuequan; Bai, Yadong; Yu, Ping, Chip package and packaging method.
  4. Kawabata, Kenichi; Hayakawa, Toshio; Okubo, Toshiro, Electronic circuit package.
  5. Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati; Chow, Seng Guan, Encapsulant cavity integrated circuit package system and method of fabrication thereof.
  6. Gremillet, Patrick; Ledain, Bernard, Hyperfrequency housing occupying a small surface area and mounting of such a housing on a circuit.
  7. Park, Soo-San; Kwon, Hyeog Chan; Lee, Sang-Ho; Ha, Jong-Woo, Integrated circuit package system including stacked die.
  8. Pendse, Rajendra D., Integrated circuit package system including zero fillet resin.
  9. Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati; Chow, Seng Guan, Integrated circuit package system with an encapsulant cavity and method of fabrication thereof.
  10. Chow, Seng Guan; Shim, II Kwon; Han, Byung Joon, Integrated circuit package system with exposed interconnects.
  11. Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati; Chow, Seng Guan, Integrated circuit packaging system with a component in an encapsulant cavity and method of fabrication thereof.
  12. Rofougaran, Ahmadreza, Method and system for communicating via flip-chip die and package waveguides.
  13. Karnezos,Marcos, Method for making a semiconductor multi-package module having wire bond interconnect between stacked packages.
  14. Karnezos, Marcos; Carson, Flynn; Kim, Youngcheol, Method for making semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package.
  15. Karnezos,Marcos, Method of fabricating a semiconductor assembly including chip scale package and second substrate with exposed substrate surfaces on upper and lower sides.
  16. Karnezos, Marcos, Method of fabricating a semiconductor multi package module having an inverted package stacked over ball grid array (BGA) package.
  17. Karnezos,Marcos, Method of fabricating a semiconductor multi-package module having a second package substrate with an exposed metal layer wire bonded to a first package substrate.
  18. Karnezos,Marcos, Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package.
  19. Karnezos, Marcos, Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages.
  20. Karnezos, Marcos, Method of fabricating a semiconductor multipackage module including a processor and memory package assemblies.
  21. Karnezos, Marcos, Method of fabricating module having stacked chip scale semiconductor packages.
  22. Karnezos,Marcos, Module having stacked chip scale semiconductor packages.
  23. Chow, Seng Guan; Kuan, Heap Hoe, Multi-chip package system.
  24. Karnezos, Marcos, Multiple chip package module having inverted package stacked over die.
  25. Karnezos, Marcos, Multiple chip package module including die stacked over encapsulated package.
  26. Mannak, Jan Hendrik; Maatman, Ivo Antoni Gerardus, Package for microwave components.
  27. Chen, Howard E.; Read, Matthew Sean; Nguyen, Hoang Mong; LoBianco, Anthony James; Zhang, Guohao; Hoang, Dinhphuoc Vu, Racetrack design in radio frequency shielding applications.
  28. Chen, Howard E.; Read, Matthew Sean; Nguyen, Hoang Mong; LoBianco, Anthony James; Zhang, Guohao; Hoang, Dinhphuoc Vu, Racetrack layout for radio frequency isolation structure.
  29. Chen, Howard E.; Read, Matthew Sean; Nguyen, Hoang Mong; LoBianco, Anthony James; Zhang, Guohao; Hoang, Dinhphuoc Vu, Racetrack layout for radio frequency shielding.
  30. Chen, Howard E.; Read, Matthew Sean; Nguyen, Hoang Mong; LoBianco, Anthony James; Zhang, Guohao; Hoang, Dinhphuoc Vu, Radio frequency isolation structure with racetrack.
  31. Karnezos,Marcos; Shim,IL Kwon; Han,Byung Joon; Ramakrishna,Kambhampati; Chow,Seng Guan, Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides.
  32. Karnezos,Marcos, Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages.
  33. Karnezos, Marcos, Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages.
  34. Karnezos,Marcos, Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages.
  35. Karnezos,Marcos, Semiconductor multi-package module having wire bond interconnect between stacked packages.
  36. Karnezos, Marcos, Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages.
  37. Karnezos, Marcos; Carson, Flynn; Kim, Youngcheol, Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package.
  38. Karnezos,Marcos; Carson,Flynn; Kim,Youngcheol, Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package.
  39. Karnezos,Marcos; Carson,Flynn, Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides.
  40. Karnezos,Marcos; Shim,Il Kwon; Han,Byung Joon; Ramakrishna,Kambhampati; Chow,Seng Guan, Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides.
  41. Carson, Flynn, Stacked integrated circuit package system and method of manufacture therefor.
  42. Kwon, Hyeog Chan; Karnezos, Marcos, Stacked semiconductor package having adhesive/spacer structure and insulation.
  43. Okubora, Akihiko, Three-dimensional integrated device.

IPC 상위 출원인