초록 ▼

A circuit and method for trimming and simulating the effect of trimming a plurality of IC parameters. Trim signals which affect respective IC parameters are generated with respective digital-to-analog converters (DACs) in response to digital bit patterns. A parameter to be trimmed is selected, a bit

A circuit and method for trimming and simulating the effect of trimming a plurality of IC parameters. Trim signals which affect respective IC parameters are generated with respective digital-to-analog converters (DACs) in response to digital bit patterns. A parameter to be trimmed is selected, a bit pattern is applied to a DAC and a trim signal generated, and the value of the parameter that results is measured. Bit patterns are iteratively created until one is identified that brings the parameter within an acceptable range. The identified bit pattern is then permanently encoded using programmable subcircuits containing poly fuses. The bit patterns are received serially to conserve I/O pins. A number of DACs are provided to enable a number of different parameters to be simulated and trimmed. A switching network is provided that selectably switches otherwise inaccessible internal nodes to an I/O pin for measurement. The trimming circuitry. is packaged within the IC package and is operable via its I/O pins, enabling the IC's parameters to be trimmed post-assembly.

대표청구항 ▼

1. A system for trimming and simulating the effect of trimming integrated circuit (IC) parameters, comprising:an input circuit arranged to receive a digital bit pattern, a plurality of digital to analog converters (DACs), each of which produces a respective trim signal at an output in response to a

1. A system for trimming and simulating the effect of trimming integrated circuit (IC) parameters, comprising:an input circuit arranged to receive a digital bit pattern, a plurality of digital to analog converters (DACs), each of which produces a respective trim signal at an output in response to a digital bit pattern received at an input, said trim signals connected to affect respective parameters of electronic circuitry within an IC, said IC having a plurality of input/output (I/O) pins, and an interface circuit connected between said input circuit and said DACs arranged to receive a parameter select signal that selects one of said parameters to be trimmed and to apply the digital bit pattern received by said input circuit to said selected parameter's respective DAC upon receipt of a simulation bit, and to permanently apply said digital bit pattern to said DAC upon receipt of a trim bit, said input circuit, said DACs, and said interface circuit packaged together within said IC and operable via said IC's I/O pins, thereby enabling said parameters to be trimmed post-assembly.