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Molding method for BGA semiconductor chip package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B29C-045/02
  • B29C-045/14
  • B29C-070/70
출원번호 US-0418569 (1999-10-15)
발명자 / 주소
  • Kao-Yu Hsu TW
  • Chun Hung Lin TW
  • Tao-Yu Chen TW
출원인 / 주소
  • Advanced Semiconductor Engineering, Inc. TW
인용정보 피인용 횟수 : 40  인용 특허 : 11

초록

A molding method for a BGA semiconductor chip package comprising a substrate supporting an array of chips having two lines of bonding pads formed at two respective side thereof. The molding method comprises the steps of: (A) providing a molding apparatus comprising a molding die having a molding cav

대표청구항

1. A molding method for a BGA semiconductor chip package comprising a substrate supporting an array of chips each having only two lines of bonding pads formed at two opposing sides thereof, the molding method comprising the steps of:providing a molding apparatus comprising a molding die having a mol

이 특허에 인용된 특허 (11)

  1. Mess Leonard E., Ball grid array (BGA) encapsulation mold.
  2. Huang Chien Ping,TWX ; Yu Kevin,TWX ; Huang Chih Ming,TWX, Encapsulating method of substrate based electronic device.
  3. Saeki Junichi (Yokohama JPX) Kaneda Aizo (Yokohama JPX) Ozawa Masakazu (Yonezawa JPX) Nakagawa Takashi (Takasaki JPX) Nishi Kunihiko (Kokubunji JPX), Method and apparatus for encapsulating semi-conductors.
  4. Lee Shaw Wei ; Takiar Hem P. ; Drummond Fred, Method for forming a panel of packaged integrated circuits.
  5. Newman Keith G. (Sunnyvale CA), Method of making integrated circuit package having multiple bonding tiers.
  6. Woosley Alan H. (Austin TX) Downey ; Jr. Harold A. (Austin TX) Mace Everitt W. (Hutto TX), Method of packaging a semiconductor device.
  7. Chia Chok J. ; Lim Seng-Sooi ; Low Qwai H., Molded array integrated circuit package.
  8. Yoshida Isamu (Yokohama JPX) Saeki Junichi (Yokohama JPX) Tsunoda Shigeharu (Fujisawa JPX) Nishi Kunihiko (Tokyo JPX) Mitani Masao (Yokohama JPX), Resin encapsulating apparatus for semiconductor devices.
  9. Takeda Shinji,JPX, Resin-sealed type ball grid array IC package and manufacturing method thereof.
  10. Kang Je Bong,KRX ; Song Young Yee,KRX ; Sung Si Chan,KRX, Semiconductor integrated circuit device having dummy bonding wires.
  11. Lim Hong Woo,KRX, Substrate having gate recesses or slots and molding device and molding method thereof.

이 특허를 인용한 특허 (40)

  1. Ko, WonJun; Cho, NamJu, Base package system for integrated circuit package stacking and method of manufacture thereof.
  2. Donofrio, Matthew; Nordby, Howard; Andrews, Peter S., Conformally coated light emitting devices and methods for providing the same.
  3. Vinciarelli, Patrizio; LaFleur, Michael B., Encapsulation method for electronic modules.
  4. Kuo,Frank, Encapsulation method for leadless semiconductor packages.
  5. Kuo, Frank, Encapsulation techniques for leadless semiconductor packages.
  6. Ahmad,Syed Sajid, Interconnecting substrates for electrical coupling of microelectronic components.
  7. Ahmad,Syed Sajid, Interconnecting substrates for electrical coupling of microelectronic components.
  8. Oga, Akira; Inao, Hisaho; Hidaka, Hiroshi, Lead frame and method for fabricating resin-encapsulated semiconductor device.
  9. Negley, Gerald H.; Van De Ven, Antony Paul; Hunter, F. Neal, Lighting device.
  10. Chakraborty, Arpan, Low index spacer layer in LED devices.
  11. Lee, Kian Chai; Tim, Teoh Bee Yong; M, Vijendran; Choong, Lien Wah, Method and apparatus for distributing mold material in a mold for packaging microelectronic devices.
  12. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  13. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  14. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  15. Chan, Shiun-Wei; Ke, Chih-Hsun, Method for packaging light emitting diode.
  16. Ahmad, Syed Sajid, Method of Interconnecting substrates for electrical coupling of microelectronic components.
  17. Cobbley,Chad A., Method of encapsulating interconnecting units in packaged microelectronic devices.
  18. Cobbley,Chad A., Method of encapsulating packaged microelectronic devices with a barrier.
  19. Gotou, Masakatsu; Kasai, Norihiko, Method of manufacturing a semiconductor device.
  20. Hayashida, Tetsuya; Kasai, Norihiko, Method of manufacturing a semiconductor device in which a block molding package utilizes air vents in a substrate.
  21. Negley, Gerald H.; Leung, Michael, Methods of coating semiconductor light emitting elements by evaporating solvent from a suspension.
  22. Bolken, Todd O., Microelectronic devices and microelectronic die packages.
  23. Leung, Michael S.; Tarsa, Eric J.; Ibbetson, James, Molded chip fabrication method and apparatus.
  24. Leung, Michael S.; Tarsa, Eric J.; Ibbetson, James, Molded chip fabrication method and apparatus.
  25. Leung, Michael S; Tarsa, Eric J; Ibbetson, James, Molded chip fabrication method and apparatus.
  26. Shih-Chang Lee TW; Gwo Liang Weng TW, Molding apparatus and molding method for flexible substrate based package.
  27. Gerber, Mark Allen; O'Conner, Shawn Martin, Package-on-package semiconductor assembly.
  28. Cobbley, Chad A., Packaged microelectronic devices with interconnecting units.
  29. James, Stephen L.; Cobbley, Chad A., Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices.
  30. James,Stephen L.; Cobbley,Chad A., Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices.
  31. Hussell, Christopher P.; Emerson, David T., Phosphor distribution in LED lamps using centrifugal force.
  32. Hussell, Christopher P.; Emerson, David T., Phosphor distribution in LED lamps using centrifugal force.
  33. Roberts, John; Chaloupecky, Robert; You, Chenhua, Solid state array modules for general illumination.
  34. Roberts, John; Chaloupecky, Robert; You, Chenhua, Solid state linear array modules for general illumination.
  35. Farnworth, Warren M., Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece.
  36. Eing-Chieh Chen TW; Cheng-Yuan Lai TW; Tzu-Yi Tien TW, Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same.
  37. Negley, Gerald; Leung, Michael; Becerra, Maryanne; Tarsa, Eric; Andrews, Peter, Uniform emission LED package.
  38. Chitnis, Ashay; Ibbetson, James; Chakraborty, Arpan; Tarsa, Eric J.; Keller, Bernd; Seruto, James; Fu, Yankun, Wafer level phosphor coating method and devices fabricated utilizing method.
  39. Chitnis, Ashay; Ibbetson, James; Keller, Bernd; Emerson, David T.; Edmond, John; Bergmann, Michael J.; Cabalu, Jasper S.; Britt, Jeffrey C.; Chakraborty, Arpan; Tarsa, Eric; Seruto, James; Fu, Yankun, Wafer level phosphor coating method and devices fabricated utilizing method.
  40. Chakraborty, Arpan, Wafer level phosphor coating technique for warm light emitting diodes.
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