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Prefabricated semiconductor chip carrier 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
출원번호 US-0208586 (1994-03-11)
발명자 / 주소
  • Stanford W. Crane, Jr.
  • Maria M. Portuondo
출원인 / 주소
  • Silicon Bandwidth Inc.
대리인 / 주소
    Morgan, Lewis & Bockius LLP
인용정보 피인용 횟수 : 12  인용 특허 : 48

초록

A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that

대표청구항

1. A semiconductor die carrier comprising:a substrate adapted for holding a semiconductor die, the substrate including a plurality of electrically insulative side walls defining an exterior surface of said substrate; and a plurality of preformed, substantially L-shaped conductive leads frictionally

이 특허에 인용된 특허 (48)

  1. Frei John K. (Mesa AZ) Brice-Heames Kenneth (Mesa AZ), Apparatus for adapting semiconductor die pads and method therefor.
  2. Hundt Michael J. (Double Oak TX), Circuit assembly having interposer lead frame.
  3. Sucheski Matthew M. (Harrisburg PA) Barkus Lee A. (Millersburg PA), Coaxial contact element.
  4. Kochanski Ronald P. (Arlington Heights IL) Schmidt Detlef W. (Schaumburg IL), Device with captivate chip capacitor devices and method of making the same.
  5. Gatto Donald F. (Sunrise FL) Milciunas Juan (Ft. Lauderdale FL), Dual electronic component assembly.
  6. Kondo Mitsuhiro (Oogaki JPX) Watanabe Osamu (Oogaki JPX), Encapsulated semiconductor device with bridge sealed lead frame.
  7. Sugimoto Masahiro (Yokosuka JPX) Wakasugi Yasumasa (Kawasaki JPX) Harada Shigeki (Kawasaki JPX), Heatsink package for flip-chip IC.
  8. Shaheen Joseph M. (La Habra CA) Yamaguchi James S. (Lake Forest CA), Hermetic organic/inorganic interconnection substrate for hybrid circuit manufacture.
  9. Frankeny, Jerome A.; Frankeny, Richard F.; Haj-Ali-Ahmadi, Javad; Hermann, Karl; Imken, Ronald L., High density interconnect strip.
  10. Desai Kishor V. (Vestal NY) Macek Thomas G. (Endicott NY) Patel Maganlal S. (Endicott NY) Thomas Edwin L. (Apalachin NY), High density, separable connector and contact for use therein.
  11. Sugano Toshio (Kodaira JPX) Tsukui Seiichiro (Kawagoe JPX), High packing density module board and electronic device having such module board.
  12. Boucard Michel R. J. (Tournefeuille FRX) Francois Thirion C. (Auterive FRX), Housing for an electronic circuit.
  13. Salera Edmond A. (Santa Barbara CA), Hybrid microelectronic circuit package.
  14. Krumme John F. (Woodside CA) Hodgson Darel E. (Palo Alto CA), Integrated circuit package and seal therefor.
  15. Tukamoto Takashi (Suwa JPX) Abe Sachiyuki (Suwa JPX) Yabushita Tetsuo (Suwa JPX) Hayashi Yoshimitsu (Suwa JPX), Integrated circuit package for flexible computer system alternative architectures.
  16. Papageorge Marc V. (Boca Raton FL) Freyman Bruce J. (Boca Raton FL) Juskey Frank J. (Coral Spring FL) Thome John R. (Palatine IL), Integrated circuit package having a face-to-face IC chip arrangement.
  17. Nelson Gregory H. (Gilbert AZ) Lebow Sanford (Westlake CA) Nogavich Eugene (Gilbert AZ), Interconnect device and method of manufacture thereof.
  18. Masayuki Watanabe (Yokohama JPX) Toshio Sugano (Kokubunji JPX) Seiichiro Tsukui (Komoro JPX) Takashi Ono (Akita JPX) Yoshiaki Wakashima (Kawasaki JPX), Lead connections means for stacked tab packaged IC chips.
  19. Shaffer Howard R. (Millersburg PA), Limited insertion force contact terminals and connectors.
  20. Krum Alvin L. (Huntington Beach CA) Conklin Charles W. (Huntington Beach CA), Low resistance electrical interconnection for synchronous rectifiers.
  21. Gregoire George D. (9927 Aviary Dr. San Diego CA 92131), Method and apparatus for making printed circuit boards.
  22. Kobayashi Yasushi (Kamikodanaka JPX) Kogure Seiji (Nakahara JPX), Method for encapsulting IC chip.
  23. Gregoire George D. (9927 Aviary Dr. San Diego CA 92131), Method for making printed circuit boards.
  24. Hingorany Prem R. (Broomfield CO), Method of manufacture power hybrid microcircuit.
  25. Gregoire George D. (San Diego CA), Method of mounting a surface-mountable IC to a converter board.
  26. Gates ; Jr. Louis E. (Westlake Village CA) Kamensky Albert (Redondo Beach CA) Devendorf Don C. (Los Angeles CA), Microelectronic package.
  27. Reylek Robert S. (St. Paul MN) Thompson Kenneth C. (St. Paul MN), Miniature multiple conductor electrical connector.
  28. Taniuchi Kenjiro (Kawasaki JPX) Miyazawa Hideo (Kawasaki JPX) Ishikawa Kouji (Kawasaki JPX) Watanabe Kouji (Kawasaki JPX), Mounting device for mounting an electronic device on a substrate by the surface mounting technology.
  29. Martens John D. (Plano TX) Ammon J. Preston (Dallas TX), Multi row high density connector.
  30. Feng Bai-Cwo (Tarrytown NY) Feng George C. (Fishkill NY) McMaster Richard H. (Wappingers Falls NY), Multi-layer package incorporating a recessed cavity for a semiconductor chip.
  31. Hirano Naohiko (Yokohama JPX), Multilayer package.
  32. Tillotson John (Southfield MI), Multiple contact header assembly.
  33. Selinko George J. (Lighthouse Point FL), Non-hermetically sealed stackable chip carrier package.
  34. Ingram Arthur J. (Allentown PA) Weingrod Irving (Allentown PA), Package for semiconductor integrated circuits.
  35. Buck Jonathan E. (Harrisburg PA) Rose William H. (Harrisburg PA), Paired contact electrical connector system.
  36. Shirling David J. (Waterbury CT), Pin grid array having seperate posts and socket contacts.
  37. Kohno Ryuji (Ibaraki JPX) Nishimura Asao (Ushiku JPX) Kitano Makoto (Tsuchiura JPX) Yaguchi Akihiro (Ibaraki JPX) Yoneda Nae (Ibaraki JPX), Plastic-molded-type semiconductor device.
  38. Sakemi Shouzi (Fukuoka JPX) Sakai Tadahiko (Fukuoka JPX), Printed circuit board.
  39. Ammon J. Preston (Dallas TX) Weaver Harry R. (Dallas TX) Evans Evan J. (Plano TX), Printed circuit board finger connector.
  40. Hashemi Seyed H. (Austin TX) Olla Michael A. (Austin TX) Parker John C. (Round Rock TX), Process for manufacturing a stacked multiple leadframe semiconductor package using an alignment template.
  41. Utunomiya Jiro (Tokyo JPX) Iida Saburo (Tokyo JPX) Sibuya Hitosi (Tokyo JPX) Kusaba Kazunori (Tokyo JPX) Narumi Isao (Tokyo JPX), Process of assembling terminal structure.
  42. Brown Candice H. (San Jose CA), Process of making a semiconductor device having parallel leads directly connected perpendicular to integrated circuit la.
  43. Arima Hideo (Yokohama JPX) Takeda Kenji (Kamakura JPX) Yamamura Hideho (Yokohama JPX) Kobayashi Fumiyuki (Sagamihara JPX), Semiconductor chip carrier, module having same chip carrier mounted therein, and electronic device incorporating same mo.
  44. Kohara Masanobu (Itami JPX) Kondo Takashi (Itami JPX) Yama Yomiyuki (Itami JPX), Semiconductor device and package.
  45. Jurista Thomas M. (Vestal NY) Mantilla Osvaldo A. (Endicott NY), Sequential Connecting device.
  46. Dutta Vivek B. (Cupertino CA) Demmin Jeffrey C. (Mt. View CA) DiOrio Mark L. (Cupertino CA) Ewanich Jon T. (Cupertino CA), Stadium-stepped package for an integrated circuit with air dielectric.
  47. Juskey Frank J. (Coral Springs FL) Suppelsa Anthony B. (Coral Springs FL), Thermally conductive integrated circuit package with radio frequency shielding.
  48. Nicewarner ; Jr. Earl R. (Gaithersburg MD), Three-dimensional integrated circuit package.

이 특허를 인용한 특허 (12)

  1. Strange, Andrew; Heitzman, Aaron, Alignment device for fine pitch connector leads.
  2. Xue, Xiaojie; Raleigh, Carl, Apparatus and method for microelectromechanical systems device packaging.
  3. Matayabas, Jr., James C., Dielectric film with low coefficient of thermal expansion (CTE) using liquid crystalline resin.
  4. Bolanowski, Wladyslaw; Aberg, Peter, Memory device and receptacle for electronic devices.
  5. Joshi,Rajeev; Wu,Chung Lin, Method for making a semiconductor die package.
  6. Crane, Jr., Stanford W.; Alcaria, Vicente D.; Jeon, Myoung-Soo, Micro grid array semiconductor die package.
  7. Hinkle,S. Derek; Brooks,Jerry M.; Corisis,David J., Multi-part lead frame.
  8. Tsukagoshi, Koji; Oku, Sadao; Fujita, Hiroyuki; Hayashi, Keiichiro; Akino, Masaru, Semiconductor device.
  9. Suzuki, Mikimasa; Kuroyanagi, Akira; Miyajima, Takeshi; Miura, Shoji; Tomatsu, Yutaka; Suzuki, Fuminari, Semiconductor device and method for manufacturing the same.
  10. Joshi, Rajeev; Wu, Chung-Lin, Semiconductor die including conductive columns.
  11. Martizon, Jr., Arturo; Goida, Thomas M., Two-axis vertical mount package assembly.
  12. Xue, Xiaojie, Vertical mount package and wafer level packaging therefor.
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