초록 ▼

A cache blocking mechanism ensures that transient data is not stored in a secondary cache of a router by managing a designated set of buffers in a main memory of the router. The mechanism defines a window of virtual addresses that map to predetermined physical memory addresses associated with the se

A cache blocking mechanism ensures that transient data is not stored in a secondary cache of a router by managing a designated set of buffers in a main memory of the router. The mechanism defines a window of virtual addresses that map to predetermined physical memory addresses associated with the set of buffers; in the illustrative embodiment, only transient data may be stored in these buffers. The mechanism further blocks write requests directed to these predetermined memory buffers from propagating to the secondary cache, thereby precluding storage of transient data in the cache.

대표청구항 ▼

1. A cache blocking mechanism that inhibits copying of specific data to a secondary cache means for storing during a write request executed by a processor means and directed to a main memory means for storing of a network device, the mechanism comprising:means for buffer storing the specific data in

1. A cache blocking mechanism that inhibits copying of specific data to a secondary cache means for storing during a write request executed by a processor means and directed to a main memory means for storing of a network device, the mechanism comprising:means for buffer storing the specific data in the main memory means for storing, the means for buffer storing being allocated a predetermined physical address within the main memory means for storing; a primary cache means for storing contained within the processor means and adapted to store the specific data in response to a read request executed by the processor means; means for blocking that inhibits copying of the specific data from the buffer means for storing to the secondary cache means for storing in response to decoding the predetermined physical address during the write request to the main memory means for storing; and the means for blocking including a first logical OR circuit and a second logical OR circuit, the first logical OR circuit generating a first output based upon a particular address bit of the predetermined physical address and a first write enable signal, the second logical OR circuit generating a second output based upon the particular address bit and a second write enable signal.