초록 ▼

A differential delay cell includes load transistors and a current source transistor biased linearly. The delay control input of the differential delay cell is also the power supply input such that when the power supply voltage changes, the delay in the differential delay cell changes. The resistance

A differential delay cell includes load transistors and a current source transistor biased linearly. The delay control input of the differential delay cell is also the power supply input such that when the power supply voltage changes, the delay in the differential delay cell changes. The resistance presented by the load transistors changes as a function of the power supply voltage, as does the current sourced by the variable current source. The combination of changing resistance and changing current as the power supply voltage changes results in a substantially constant output voltage swing. A ring of differential delay cells is included in a voltage controlled oscillator, which is in turn included in a phase lock loop. The phase lock loop has a wide loop bandwidth and the voltage controlled oscillator has a good power supply rejection ratio.

대표청구항 ▼

1. A differential delay cell comprising:a first input transistor and a second input transistor; a first load transistor coupled drain to source between the first input transistor and a delay control input node, the first load transistor having a first gate; a first resistor coupled between the first

1. A differential delay cell comprising:a first input transistor and a second input transistor; a first load transistor coupled drain to source between the first input transistor and a delay control input node, the first load transistor having a first gate; a first resistor coupled between the first gate and a reference node; a second load transistor coupled drain to source between the second input transistor and the delay control input node, the second load transistor having a second gate; a second resistor coupled between the second gate and the reference node; and a variable current source coupled between the first and second input transistors and the reference node, the variable current source being configured such that a current sourced by the variable current source changes responsive to changes in voltage on the delay control input node.