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특허 상세정보

Methods and apparatus for shallow trench isolation

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) C23C-016/52    C23C-016/22    G05B-019/00    G05D-007/00    G05D-011/02   
미국특허분류(USC) 118/697; 118/715; 118/725; 700/095; 700/108; 700/121; 700/266; 700/275; 700/282
출원번호 US-0613934 (2000-07-11)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Townsend & Townsend & Crew
인용정보 피인용 횟수 : 62  인용 특허 : 14
초록

The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention ...

대표
청구항

1. A substrate processing system comprising:a vacuum chamber, said vacuum chamber operable at a pressure between about 10-760 torr; a gas distribution manifold, located within said housing, to introduce reactive gases into said vacuum chamber; a ceramic heater to hold a wafer, said ceramic heater heating to a temperature of greater than about 500.degree. C.; means for causing deposition of an insulating layer comprising undoped silicate glass (USG) at said temperature of greater than about 500.degree. C. on said wafer from a reaction of silicon and oxyge...

이 특허에 인용된 특허 (14)

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  7. Gupta Anand ; Rana Virendra V. S. ; Verma Amrita ; Bhan Mohan K. ; Subrahmanyam Sudhakar. Method and apparatus for improving the film quality of plasma enhanced CVD films at the interface. USP2000096121163.
  8. Rana Virendra V. S. ; Conners Andrew ; Gupta Anand ; Guo Xin ; Hong Soonil. Method for submicron gap filling on a semiconductor substrate. USP2001026191026.
  9. Fong Gary ; Xia Li-Qun ; Nemani Srinivas ; Yieh Ellie. Methods and apparatus for cleaning surfaces in a substrate processing system. USP1998095812403.
  10. Yieh Ellie ; Xia Li-Qun ; Gee Paul ; Nguyen Bang. Methods and apparatus for forming ultra-shallow doped regions using doped silicon oxide films. USP2000086099647.
  11. Yieh Ellie ; Xia Li-Qun ; Nemani Srinivas. Methods for shallow trench isolation. USP2000096114216.
  12. Fong Gary ; Silvestre Irwin. Substrate processing apparatus with bottom-mounted remote plasma system. USP1999085935334.
  13. Guo Ted ; Cohen Barney M. ; Verma Amrita. Thermal post-deposition treatment of halogen-doped films to improve film stability and reduce halogen migration to inter. USP1998065763010.
  14. Guo Ted ; Cohen Barney M. ; Verma Amrita. Thermal post-deposition treatment of halogen-doped films to improve film stability and reduce halogen migration to interconnect layers. USP2000066079354.

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