초록 ▼

A method for making a ULSI MOSFET chip includes forming a transistor gate on a substrate and defining the contours of shallow source/drain extensions by implanting a first pre-amorphization (PAI) substance into the substrate. A sidewall spacer is then formed on the substrate next to the gate, and a

A method for making a ULSI MOSFET chip includes forming a transistor gate on a substrate and defining the contours of shallow source/drain extensions by implanting a first pre-amorphization (PAI) substance into the substrate. A sidewall spacer is then formed on the substrate next to the gate, and a second PAI substance is implanted into the substrate to defame the contours of a deep source/drain junction. Then, a dopant is provided on the surface of the substrate, and the portions of the substrate that contain PAI substances are silicidized to render the portions relatively more absorbing of laser energy. These pre-amorphized portions are then annealed by laser to melt only the pre-amorphized portions. During melting, the dopant is driven from the surface of the substrate into the pre-amorphized portions to thereby establish source/drain regions below the gate.

대표청구항 ▼

1. A method for establishing at least one transistor on a semiconductor device, comprising:forming at least one gate on a semiconductor substrate, each at least one gate having a gate region, each at least one gate having formed thereon a protective cap, each at least one gate having a source region

1. A method for establishing at least one transistor on a semiconductor device, comprising:forming at least one gate on a semiconductor substrate, each at least one gate having a gate region, each at least one gate having formed thereon a protective cap, each at least one gate having a source region and a drain region laterally disposed in the substrate; implanting a first pre-amorphization material in at least one first region of the substrate, the at least one first region being shallow in a depth range no greater than 30 nm, the protective cap preventing the first pre-amorphization material from being implanted into the gate, the at least one gate and the at least one protective cap patterning the first pre-amorphization material implantation; forming at least one sidewall spacer disposed laterally to the at least one gate; implanting a second pre-amorphization material in at least one second region of the substrate, the at least one second region being deep in a depth range greater than 30 nm, the protective cap preventing the second pre-amorphization material from being implanted into the at least one gate, the at least one sidewall spacer patterning the second pre-amorphization material implantation; stripping the at least one protective cap; depositing at least one dopant onto the at least one source region, the at least one drain region, and the at least one gate region; depositing at least one refractory metal onto the at least one source region, the at least one drain region, and the at least one gate region; silicidizing, by reacting, the at least one refractory metal with a plurality of silicon (Si) ions from the at least one source region, the at least one drain region, and the at least one gate region, thereby forming at least one refractory metal silicide on the dopant in the at least one first region and the at least one gate region; and annealing, by lasing, the at least one silicide, whereby the at least one silicide provides at least one heat sink for preferentially absorbing laser energy, and whereby laser energy absorption by the at least one silicide transfers heat for melting (amorphizing) the at least one first region and the at least one second region, for heating the at least one gate region, thereby facilitating migration of the at least one dopant away from the at least one silicide and down into the at least one amorphized first region, the at least one amorphized second region, and the at least one heated gate region, and thereby respectively forming at least one shallow source/drain extension in a depth range no greater than 30 nm, at least one deep source/drain contact junction in a depth range greater than 30 nm, and at least one doped gate.