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[미국특허] Probe card, test method and test system for semiconductor wafers 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/26
  • G01R-031/02
출원번호 US-0394960 (1999-09-10)
발명자 / 주소
  • Salman Akram
  • C. Patrick Doherty
  • Warren M. Farnworth
  • David R. Hembree
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Stephen A. Gratton
인용정보 피인용 횟수 : 54  인용 특허 : 36

초록

A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; patterns of pin contacts slidably mounted to the substrate; and a force applying member for biasing the pin contacts into electrical contact w

대표청구항

1. A method for testing a semiconductor wafer having a plurality of contacts comprising:providing a probe card comprising a substrate having a plurality of openings, a plurality of electrically conductive pins slidably mounted in the openings for movement in a Z direction, and a force applying membe

이 특허에 인용된 특허 (36) 인용/피인용 타임라인 분석

  1. Krivy Andrew J. ; Farnworth Warren M. ; Hembree David R. ; Akram Salman ; Wark James M. ; Jacobson John O., Calibration target for calibrating semiconductor wafer test systems.
  2. Akram Salman ; Wark James M. ; Farnworth Warren M., Direct connect interconnect for testing semiconductor dice and wafers.
  3. Hembree David R. ; Farnworth Warren M. ; Wark James M., Force applying probe card and test system for semiconductor wafers.
  4. Hembree David R. ; Jacobson John O. ; Wark James M. ; Farnworth Warren M. ; Akram Salman ; Wood Alan G., Interconnect for making temporary electrical connections with bumped semiconductor components.
  5. Akram Salman ; Farnworth Warren M., Interconnect with pressure sensing mechanism for testing semiconductor wafers.
  6. Akram Salman ; Farnworth Warren M., Interconnect with pressure sensing mechanism for testing semiconductor wafers.
  7. Huff Richard E. (Belmont CA), Membrane probe contact bump compliancy system.
  8. Liu Ken K. F. (Saratoga CA) Min Byoung-Youl (Cupertino CA) Moti Robert J. (San Jose CA) Husain Syed A. (Milpitas CA), Membrane probing of circuits.
  9. Liu Ken Kuang-Fu ; Min Byoung-Youl ; Sano Kunio,JPX ; Sato Takashi,JPX, Membrane probing of circuits.
  10. Akram Salman ; Farnworth Warren M. ; Wood Alan G., Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate.
  11. Akram Salman ; Farnworth Warren M. ; Wood Alan G., Method for fabricating semiconductor components using focused laser beam.
  12. Elder Richard A. (Dallas TX) Wilson Arthur M. (Dallas TX) Bagen Susan V. (Dallas TX) Miller Juanita G. (Richardson TX), Method for fabrication of probe card for testing of semiconductor devices.
  13. Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Wood Alan G. (Boise ID), Method for forming contact pins for semiconductor dice and interconnects.
  14. Tada Tetsuo (Hyogo JPX) Takagi Ryouichi (Hyogo JPX), Method of manufacturing a probing card for wafer testing.
  15. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of planarizing tips of probe elements of a probe card assembly.
  16. Akram Salman ; Hembree David R. ; Wood Alan G., Micromachined probe card having compliant contact members for testing semiconductor wafers.
  17. Swapp Mavin (Mesa AZ), Micromachined semiconductor probe card.
  18. Akram Salman ; Hembree David R. ; Wood Alan G., Micromachined silicon probe card for semiconductor dice and method of fabrication.
  19. Iino Shinji (Yamanashi JPX) Kubota Tamio (Kofu JPX) Yokota Keiichi (Nirasaki JPX), Probe card.
  20. Hembree David R. ; Farnworth Warren M. ; Akram Salman ; Wood Alan G. ; Doherty C. Patrick ; Krivy Andrew J., Probe card and testing method for semiconductor wafers.
  21. Hagihara Junichi,JPX, Probe card device used in probing apparatus.
  22. Hembree David R. ; Farnworth Warren M. ; Akram Salman ; Wood Alan G. ; Doherty C. Patrick ; Krivy Andrew J., Probe card for semiconductor wafers and method and system for testing wafers.
  23. Liu Jui-Hsiang (Chandler AZ) Olsen Dennis R. (Scottsdale AZ), Probe card for testing unencapsulated semiconductor devices.
  24. Doherty C. Patrick ; deVarona Jorge L. ; Akram Salman, Probe card having on-board multiplex circuitry for expanding tester resources.
  25. Akram Salman ; Doherty C. Patrick ; Farnworth Warren M. ; Hembree David R., Probe card, test method and test system for semiconductor wafers.
  26. Yoshizawa Tetsuo (Yokohama JPX) Imaizumi Masaaki (Tokyo JPX) Nishida Hideyuki (Kawasaki JPX) Kondo Hiroshi (Ohsaka JPX) Sakaki Takashi (Tokyo JPX) Ichida Yasuteru (Machida JPX) Konishi Masaki (Ebina , Probe method for measuring part to be measured by use thereof and electrical circuit member.
  27. Kitamura Yoshisuke (Yamanashi-ken JPX) Nagasaka Munetoshi (Yamanashi-ken JPX), Probe test apparatus.
  28. Sano Kunio,JPX, Probing method and device with contact film wiper feature.
  29. Sano Kunio (Yamanashi-ken JPX), Probing test apparatus.
  30. Farnworth Warren M. ; Wood Alan G. ; Brooks Mike, Semiconductor package including flex circuit, interconnects and dense array external contacts.
  31. Hembree David R. ; Akram Salman, Semiconductor probe card having resistance measuring circuitry and method fabrication.
  32. Hembree David R. ; Akram Salman, Semiconductor probe card having resistance measuring circuitry and method of fabrication.
  33. Reid Lee R. (Plano TX) Cody Tommy D. (Garland TX), Solid state multiprobe testing apparatus.
  34. Hembree David R. ; Jacobson John O. ; Wark James M. ; Farnworth Warren M. ; Akram Salman ; Wood Alan G., System and interconnect for making temporary electrical connections with bumped semiconductor components.
  35. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Temporary package, system, and method for testing semiconductor dice and chip scale packages.
  36. Vinh Nguyen T., Variable contact pressure probe.

이 특허를 인용한 특허 (54) 인용/피인용 타임라인 분석

  1. Brunner,Matthias, Apparatus and method for contacting of test objects.
  2. Kirby,Kyle K.; Farnworth,Warren M.; Wark,James M.; Hiatt,William M.; Hembree,David R.; Wood,Alan G., Compliant contact pin assembly and card system.
  3. Kirby,Kyle K.; Farnworth,Warren M.; Wark,James M.; Hiatt,William M.; Hembree,David R.; Wood,Alan G., Compliant contact pin assembly and card system.
  4. Kirby,Kyle K.; Farnworth,Warren M.; Wark,James M.; Hiatt,William M.; Hembree,David R.; Wood,Alan G., Compliant contact pin assembly, card system and methods thereof.
  5. Kirby,Kyle K.; Farnworth,Warren M.; Wark,James M.; Hiatt,William M.; Hembree,David R.; Wood,Alan G., Compliant contact pin test assembly and methods thereof.
  6. Brunner, Matthias; Kurita, Shinichi; Schmid, Ralf; Abboud, Fayez (Frank) E.; Johnston, Benjamin; Bocian, Paul; Beer, Emanuel, Configurable prober for TFT LCD array test.
  7. Brunner,Matthias; Kurita,Shinichi; Schmid,Ralf; Abboud,Fayez E.; Johnston,Benjamin; Bocian,Paul; Beer,Emanuel, Configurable prober for TFT LCD array test.
  8. Brunner,Matthias; Kurita,Shinichi; Schmid,Ralf; Abboud,Fayez (Frank) E.; Johnston,Benjamin; Bocian,Paul; Beer,Emanuel, Configurable prober for TFT LCD array testing.
  9. Mok, Sammy; Chong, Fu Chiung, Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies.
  10. Kirby,Kyle K.; Farnworth,Warren M.; Wark,James M.; Hiatt,William M.; Hembree,David R.; Wood,Alan G., Contact pin assembly and contactor card.
  11. Zhou, Yu; Yu, David; Aldaz, Robert Edward; Khoury, Theodore A., Contact structure and production method thereof and probe contact assembly using same.
  12. Zhou, Yu; Yu, David; Aldaz, Robert Edward; Khoury, Theodore A., Contact structure production method.
  13. Zhou, Yu; Yu, David; Aldaz, Robert Edward; Khoury, Theodore A., Contact structure production method.
  14. Beaman,Brian S.; Chiu,George Liang Tai; Fogel,Keith; Lauro,Paul A.; Morris,Daniel P.; Shih,Da Juan, Electrical connector design and contact geometry and method of use thereof and methods of fabrication thereof.
  15. Haemer,Joseph Michael; Chong,Fu Chiung; Modlin,Douglas N., Enhanced compliant probe card systems having improved planarity.
  16. Bottoms, Wilmer R.; Chong, Fu Chiung; Mok, Sammy; Modlin, Douglas, High density interconnect system for IC packages and interconnect assemblies.
  17. Chong, Fu Chiung; Kao, Andrew; McKay, Douglas; Litza, Anna; Modlin, Douglas; Mok, Sammy; Parekh, Nitin; Swiatowiec, Frank John; Shan, Zhaohui, High density interconnect system having rapid fabrication cycle.
  18. Chong, Fu Chiung; Kao, Andrew; McKay, Douglas; Litza, Anna; Modlin, Douglas; Mok, Sammy; Parekh, Nitin; Swiatowiec, Frank John; Shan, Zhaohui, High density interconnect system having rapid fabrication cycle.
  19. Chong,Fu Chiung; Kao,Andrew; McKay,Douglas; Litza,Anna; Modlin,Douglas; Mok,Sammy; Parekh,Nitin; Swiatowiec,Frank John; Shan,Zhaohui, High density interconnect system having rapid fabrication cycle.
  20. Hartnett, Fred, In-circuit testing system and method.
  21. Lewinnek, David Walter; Sinsheimer, Roger Allen; Valiente, Luis Antonio; DiPalo, Craig Anthony, Interconnect for transmitting signals between a device and a tester.
  22. Chong, Fu Chiung; Mok, Sammy, Massively parallel interface for electronic circuit.
  23. Chong,Fu Chiung; Mok,Sammy, Massively parallel interface for electronic circuit.
  24. Chong,Fu Chiung; Mok,Sammy, Massively parallel interface for electronic circuit.
  25. Chao, Clinton Chih-Chieh; Yang, Fei-Chieh; Chen, Chun-Hsing; Wang, Mill-Jer; Huang, Sheng-Hsi; Hsu, Ming-Cheng, Method for assembling a wafer level test probe card.
  26. Farnworth, Warren M.; Wood, Alan G.; Hembree, David R., Method for fabricating semiconductor components and interconnects with contacts on opposing sides.
  27. Akram,Salman; Farnworth,Warren M.; Wood,Alan G., Method for fabricating semiconductor components by forming conductive members using solder.
  28. Hembree, David R.; Farnworth, Warren M.; Akram, Salman; Wood, Alan G.; Doherty, C. Patrick; Krivy, Andrew J., Method for testing semiconductor wafers.
  29. Kirby,Kyle K.; Farnworth,Warren M.; Wark,James M.; Hiatt,William M.; Hembree,David R.; Wood,Alan G., Method of making contact pin card system.
  30. Kirby,Kyle K.; Farnworth,Warren M.; Wark,James M.; Hiatt,William M.; Hembree,David R.; Wood,Alan G., Methods of forming a contact pin assembly.
  31. Johnston, Benjamin M.; Krishnaswami, Sriram; Nguyen, Hung T.; Brunner, Matthias; Liu, Yong, Mini-prober for TFT-LCD testing.
  32. Okumura, Katsuya; Yonezawa, Toshihiro, Probe and method of manufacturing probe.
  33. Endres, Eric; Strom, John T.; Kuwasaki, Christian; McLaughlin, Christopher, Probe card analysis system and method.
  34. Hembree,David R.; Farnworth,Warren M.; Akram,Salman; Wood,Alan G.; Doherty,C. Patrick; Krivy,Andrew J., Probe card for semiconductor wafers having mounting plate and socket.
  35. Wood, Alan G.; Doan, Trung T.; Hembree, David R., Probe card for testing microelectronic components.
  36. Kirby, Kyle K., Probe card for use with microelectronic components, and methods for making same.
  37. Ku, Wei-Cheng; Lai, Jun-Liang, Probe card of low power loss.
  38. Wood, Alan G.; Doan, Trung T.; Hembree, David R., Probe card, e.g., for testing microelectronic components, and methods for making same.
  39. Krishnaswami, Sriram; Brunner, Matthias; Beaton, William; Liu, Yong; Johnston, Benjamin M.; Nguyen, Hung T.; Ledl, Ludwig; Schmid, Ralf, Prober for electronic device testing on large area substrates.
  40. Schaeffer, Ralph; Crump, Brett, Selectively configurable microelectronic probes.
  41. Schaeffer, Ralph; Crump, Brett, Selectively configurable probe structures, e.g., for testing microelectronic components.
  42. Schaeffer, Ralph; Crump, Brett, Selectively configurable probe structures, e.g., for testing microelectronic components.
  43. Schaeffer,Ralph; Crump,Brett, Selectively configurable probe structures, e.g., for testing microelectronic components.
  44. Schaeffer,Ralph; Crump,Brett, Selectively configurable probe structures, e.g., selectively configurable probe cards for testing microelectronic components.
  45. Farnworth, Warren M.; Wood, Alan G.; Hembree, David R., Semiconductor component and interconnect having conductive members and contacts on opposing sides.
  46. Akram, Salman; Farnworth, Warren M.; Wood, Alan G., Semiconductor package having interconnect with conductive members.
  47. Akram, Salman; Farnworth, Warren M.; Wood, Alan G., Stacked semiconductor package having laser machined contacts.
  48. Sinsheimer, Roger Allen, Structure for transmitting signals in an application space between a device under test and test electronics.
  49. Lin, Lee-Chung; Huang, Jun-Hao; Hsiao, Chun-Chieh, System and method for qualifying multiple device under test (DUT) test head.
  50. Mok, Sammy; Chong, Fu Chiung; Milter, Roman, Systems for testing and packaging integrated circuits.
  51. Ito, Daisuke; Nakagawa, Hiroshi; Ito, Katsutoshi; Shinonaga, Naoyuki; Senba, Shinji, Test board for testing semiconductor device.
  52. Suto, Anthony J.; Wrinn, Joseph Francis; Toscano, John P.; Arena, John Joseph, Test fixture.
  53. Zaerpoor,Koorosh, Ultra-short low-force vertical probe test head.
  54. Zaerpoor,Koorosh, Ultra-short low-force vertical probe test head and method.

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