이 특허에 인용된 특허 (11) 인용/피인용 타임라인 분석

1. Griffith David (Layton UT) Jones David (Layton UT) Bracken Allen T. (Layton UT) Rawlings Theon (Layton UT), Drawer loading removable cartridge disk drive.

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2. Cordoba Michael V. (Colorado Springs CO) Hardee Kim C. (Colorado Springs CO), High voltage generator having a self-timed clock circuit and charge pump, and a method therefor.

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3. Hamamoto Takeshi,JPX, Internal potential generating circuit and boosted potential generating unit using pumping operation.

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4. Futatsuya Tomoshi,JPX ; Ohba Atsushi,JPX, Internal potential generation circuit that can output a plurality of potentials, suppressing increase in circuit area.

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5. Javanifard Jahanshir J. (Sacramento CA), Low power pulse generator for smart voltage flash eeprom.

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6. Tedrow Kerry D. (Orangevale CA) Galindo Cesar (Stockton CA), Method and apparatus for controlling the output voltage provided by a charge pump circuit.

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7. Nakamura Toru (Kagoshima JPX) Ishikawa Katsuya (Kawasaki JPX), Power line connection circuit and power line switch IC for the same.

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8. Kaneko Tetsuya,JPX, Semiconductor memory device.

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9. Kim Young-Bae,KRX ; Hwang Hong-Sun,KRX, Variable output voltage booster circuits and methods.

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10. Naganawa Koji,JPX, Voltage booster circuit.

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11. Caser Fabio Tassan,ITX ; Schippers Stefan,ITX ; Cane Marcello,ITX, Voltage regulator for semiconductor non-volatile electrically programmable memory device.

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이 특허를 인용한 특허 (25) 인용/피인용 타임라인 분석

1. Ho, Hsin-Yi; Kuo, Nai-Ping; Hung, Chun-Hsiung; Chen, Gin-Laing; Ho, Wen-Chiao; Liou, Ho-Chun, Apparatus and system for reading non-volatile memory with dual reference cells.

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2. Tanzawa, Toru; Miyaba, Takeshi; Atsumi, Shigeru, Boosted voltage generating circuit and semiconductor memory device having the same.

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3. Tanzawa, Toru; Miyaba, Takeshi; Atsumi, Shigeru, Boosted voltage generating circuit and semiconductor memory device having the same.

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4. Tanzawa,Toru; Miyaba,Takeshi; Atsumi,Shigeru, Boosted voltage generating circuit and semiconductor memory device having the same.

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5. Tanzawa,Toru; Miyaba,Takeshi; Atsumi,Shigeru, Boosted voltage generating circuit and semiconductor memory device having the same.

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6. Tanzawa,Toru; Miyaba,Takeshi; Atsumi,Shigeru, Boosted voltage generating circuit and semiconductor memory device having the same.

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7. Toru Tanzawa JP; Takeshi Miyaba JP; Shigeru Atsumi JP, Boosted voltage generating circuit and semiconductor memory device having the same.

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8. Bringivijayaraghavan, Venkatraghavan, Bulk node biasing method and apparatus.

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9. Reddy, Gooty Sukumar; Kumar, Potnuru Venkata Pradeep; Yadala, Sridhar, Dynamic clock period modulation scheme for variable charge pump load currents.

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10. Huynh, Jonathan; Choi, Steve; Park, Jongmin, Dynamic load matching charge pump for reduced current consumption.

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11. Sivero,Stefano; Bedarida,Lorenzo; Frulio,Massimiliano, High precision digital-to-analog converter with optimized power consumption.

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12. Reddy, Gooty Sukumar; Kumar, Potnuru Venkata Pradeep; Yadala, Sridhar, High voltage generation using low voltage devices.

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13. Lee, Joo Sang, Internal power voltage generator of semiconductor device.

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14. Daga,Jean Michel, Method and apparatus for a dual power supply to embedded non-volatile memory.

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15. Daga,Jean Michel, Method and apparatus for a dual power supply to embedded non-volatile memory.

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16. Das, Mrinal, Method and system for signal dependent boosting in sampling circuits.

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17. Kawagoshi,Hirokazu, Power supply circuit.

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18. Reddy, Gooty Sukumar; Yadala, Sridhar, Selective body bias for charge pump transfer switches.

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19. Nakano, Takeshi; Ogawa, Mikio, Semiconductor device for short-circuiting output terminals of two or more voltage generator circuits at read time and control method for the same.

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20. Yamazaki, Shunpei; Kawamata, Ikuko; Arai, Yasuyuki, Semiconductor device including a memory.

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24. Uchikoba, Toshitaka; Yamasaki, Yuji; Origasa, Kenichi; Ohta, Kiyoto, Semiconductor integrated circuit device and method of manufacturing the same.

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25. Kwon,Myeong Ju; Lee,Jae Jin, Voltage generator with reduced noise.

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