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[미국특허] Methods and apparatus for instruction addressing in indirect VLIW processors 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/00
출원번호 US-0350191 (1999-07-09)
발명자 / 주소
  • Edwin F. Barry
  • Gerald G. Pechanek
출원인 / 주소
  • BOPS, Incorporated
대리인 / 주소
    Priest & Goldstein, PLLC
인용정보 피인용 횟수 : 53  인용 특허 : 5

초록 ▼

An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed length. The second instruction memory (VIM), contains very-long-instruction-words (VLIWs) which allow executi

대표청구항 ▼

1. An apparatus including a plurality of addressing modes for providing indirect access to very long instruction words (VLIWs) allowing both sequential code and parallel operations in the form of VLIWs to be encoded efficiently, wherein the sequential code comprising a sequence of short instruction

이 특허에 인용된 특허 (5) 인용/피인용 타임라인 분석

  1. Pechanek Gerald G. (Cary NC) Larsen Larry D. (Raleigh NC) Glossner Clair John (Durham NC) Vassiliaadis Stamatis (Zoetermeer NLX), Array processor communication architecture with broadcast processor instructions.
    상세보기
  2. Yoshida Toyohiko,JPX, Data processor having an instruction decoder and a plurality of executing units for performing a plurality of operations.
    상세보기
  3. Pechanek Gerald G. ; Drabenstott Thomas L. ; Revilla Juan Guillermo ; Strube David Carl ; Morris Grayson, Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication.
    상세보기
  4. Pechanek Gerald G. (Cary NC) Glossner Clair John (Durham NC) Larsen Larry D. (Raleigh NC) Vassiliadis Stamatis (Zoetermeer NLX), Parallel processing system and method using surrogate instructions.
    상세보기
  5. Nakano Hiraku,JPX, Variable word length very long instruction word instruction processor with word length register or instruction number r.
    상세보기

이 특허를 인용한 특허 (53) 인용/피인용 타임라인 분석

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
    상세보기
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
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  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
    상세보기
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
    상세보기
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
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  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
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  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
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  16. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
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  17. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
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  18. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
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  19. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
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  20. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
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  21. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
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  22. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
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  23. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
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  24. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  25. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  26. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  27. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
    상세보기
  28. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
    상세보기
  29. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
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  30. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
    상세보기
  31. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
    상세보기
  32. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
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  33. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  34. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  35. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  36. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  37. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  38. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  39. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  40. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  41. Cary Ussery ; Oz Levia ; Raymond Ryan, Method of generating application specific integrated circuits using a programmable hardware architecture.
    상세보기
  42. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
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  43. Moller, Christian Henrik Luja; Busboom, Carl Donald; Schneider, Dale Edward, Methods and apparatus for improved efficiency in pipeline simulation and emulation.
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  44. Barry, Edwin F.; Pechanek, Gerald G., Methods and apparatus for instruction addressing in indirect VLIW processors.
    상세보기
  45. Wolrich, Gilbert; Adiletta, Matthew; Wheeler, William R., Processor having a dedicated hash unit integrated within.
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  46. Perry, Steven, Processor with cycle offsets and delay lines to allow scheduling of instructions through time.
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  47. Heishi, Taketo; Takayama, Shuichi; Tanaka, Tetsuya; Ogawa, Hajime; Higaki, Nobuo, Processor, compiler and compilation method.
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  48. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
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  49. Wolrich, Gilbert; Adiletta, Matthew J; Wheeler, William R.; Bernstein, Debra; Hooper, Donald F., Register set used in multithreaded parallel processor architecture.
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  50. Master,Paul L.; Watson,John, Storage and delivery of device features.
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  51. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
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  52. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
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  53. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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