초록 ▼

The inventor devised methods of forming interconnects that result in conductive structures with fewer voids and thus reduced electrical resistance. One embodiment of the method starts with an insulative layer having holes and trenches, fills the holes using a selective electroless deposition, and fi

The inventor devised methods of forming interconnects that result in conductive structures with fewer voids and thus reduced electrical resistance. One embodiment of the method starts with an insulative layer having holes and trenches, fills the holes using a selective electroless deposition, and fills the trenches using a blanket deposition. Another embodiment of this method adds an anti-bonding material, such as a surfactant, to the metal before the electroless deposition, and removes at least some the surfactant after the deposition to form a gap between the deposited metal and interior sidewalls of the holes and trenches. The gap serves as a diffusion barrier. Another embodiments leaves the surfactant in place to serve as a diffusion barrier. These and other embodiments ultimately facilitate the speed, efficiency, or fabrication of integrated circuits.

대표청구항 ▼

1. An interconnect structure in an integrated circuit, comprising:an insulative layer having one or more holes or trenches, with each hole or trench having at least one sidewall; and one or more metal structures, each comprising one or more surfactants and having a portion lying at least partly with

1. An interconnect structure in an integrated circuit, comprising:an insulative layer having one or more holes or trenches, with each hole or trench having at least one sidewall; and one or more metal structures, each comprising one or more surfactants and having a portion lying at least partly within one of the holes or trenches.