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Method and apparatus for determining a processor failure in a multiprocessor computer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
출원번호 US-0196463 (1998-11-19)
발명자 / 주소
  • Kenneth A. Jansen
  • Sompong P. Olarig
  • John E. Jenne
출원인 / 주소
  • Compaq Computer Corporation
대리인 / 주소
    Akin, Gump, Strauss, Hauer & Feld, LLP
인용정보 피인용 횟수 : 32  인용 특허 : 18

초록

A multiprocessor computer includes a fault detection scheme which detects and identifies the failure of one of the processors. Each processor is assigned a write location, which may be a unique register. During normal computer operation, each processor intermittently performs a test and stores the r

대표청구항

1. A method of determining a processor failure in a multiprocessor computer, the method comprising the acts of:(a) identifying each processor in the computer; (b) assigning a unique write location to each identified processor; (c) directing each processor to perform a given test and to store a resul

이 특허에 인용된 특허 (18)

  1. Goodrum Alan L. (Tomball TX) Kotzur Gary B. (Spring TX) Lantz Kurt C. (Spring TX) Heinrich David F. (Tomball TX) Wilson Jeffrey T. (Houston TX), Circuit for reassigning the power-on processor in a multiprocessing system.
  2. Burckhartt David M. (Houston TX) Perez Lazaro D. (Houston TX) Emerson Theodore F. (Houston TX) Dow Randolph O. (Cypress TX) Stimac Gary A. (Montgomery TX), Computer failure recovery and alert system.
  3. Burckhartt David M. (Houston TX) Perez Lazaro D. (Houston TX) Emerson Theodore F. (Houston TX) Dow Randolph O. (Cypress TX) Stimac Gary A. (Montgomery TX), Computer failure recovery and alert system.
  4. Gregor Steven L. (Endicott NY) Lee Victor S. (Endicott NY), Direct hardware error identification method and apparatus for error recovery in pipelined processing areas of a computer.
  5. Horst Robert W. ; Baker William Edward ; Banton Randall G. ; Brown John Michael ; Bruckert William F. ; Bunton William Patterson ; Campbell Gary F. ; Coddington John Deane ; Cutts ; Jr. Richard W. ; , Fail-fast, fail-functional, fault-tolerant multiprocessor system.
  6. Ohguro Hiroshi,JPX ; Ikeda Koichi,JPX ; Nishiyama Takaaki,JPX ; Iwamoto Hiroshi,JPX ; Kurosawa Kenichi,JPX ; Nakamikawa Tetsuaki,JPX ; Morioka Michio,JPX, Fault recovering system provided in highly reliable computer system having duplicated processors.
  7. Nota Tadashi,JPX ; Yoshioka Masaichiro,JPX ; Nagai Seiji,JPX ; Tanaka Shunji,JPX ; Kinoshita Toshiyuki,JPX, Fault recovery method and apparatus.
  8. Hemphill John M. (Spring TX) Stewart Gregory Mart (Houston TX) Lawler Thomas S. (Houston TX), Fault tolerant multiple network servers.
  9. Hemphill John M. ; Stewart Gregory Mart ; Lawler Thomas S., Fault tolerant multiple network servers.
  10. Horst Robert W., Logical, fail-functional, dual central processor units formed from three processor units.
  11. Desmond John P. (1954 SE. Quail Cir. Hillsboro OR 97124) Ford Douglas W. (283 NE. 34th Pl. Hillsboro OR 97124) Fossey Michael E. (2320 22nd Ave. Forest Grove OR 97116) Stanbro Michael (7850 SW. Hemlo, Method and apparatus for detecting control system data processing errors.
  12. Miller David A. ; Jansen Kenneth A. ; Culley Paul R. ; Taylor Mark ; Izquierdo Javier F., Method and apparatus for independently resetting processors and cache controllers in multiple processor systems.
  13. Takizawa Mitsuyoshi (Hadano JPX) Minamisawa Akinori (Hadano JPX) Meguro Yasushi (Hadano JPX) Tanaka Natsuro (Hadano JPX), Method and apparatus for performing change-over control to processor groups by using rate of failed processors in a para.
  14. Barrett ; Jr. Archie Don ; Mandyam Sriram Srinivasan ; O'Krafka Brian Walter ; St. Onge Brett Adam ; Ramirez Robert James, Method and system for testing a multiprocessor data processing system utilizing a plurality of event tracers.
  15. Dahbura Anton T. (Bedminster NJ) Hery William J. (Mendham NJ) Sabnani Krishan K. (Berkeley Heights NJ), Method of spare capacity use for fault detection in a multiprocessor system.
  16. Ako Hidenobu (Redmond WA), Multiple processor system and output administration method thereof.
  17. Shingo Miki,JPX, Multiprocessor system capable of isolating failure processor based on initial diagnosis result.
  18. Laws Gerald E. (Austin TX) Diefendorff Keith E. (Austin TX), Self testing data processing system with system test master arbitration.

이 특허를 인용한 특허 (32)

  1. Arabi,Tawfik; Ma,Hung Piao; Iovino,Gregory M.; Rotem,Shai; Kornfeld,Avner; Taylor,Gregory F., Arrangements having IC voltage and thermal resistance designated on a per IC basis.
  2. Arabi,Tawfik; Ma,Hung Piao; Iovino,Gregory M.; Rotem,Shai; Kornfeld,Avner; Taylor,Gregory F., Arrangements having IC voltage and thermal resistance designated on a per IC basis.
  3. Guyer, James; Barney, Brandon C.; Frangioso, Jr., Ralph C.; Daniel, Stephen, Computer system.
  4. Barraclough, Keith; Irvine, David, Content routing with rights management.
  5. Chen, Tsung-Chun, Control device for use in a power supplying apparatus including multiple processors adapted to perform separate functions associated with status monitoring and load balancing.
  6. Albanese, Michael J.; Henderson, James Roland; Barraclough, Keith; Irvine, David; Philander, Rodrigo, Data communication with remote network node.
  7. Albanese, Michael J.; Henderson, James Roland; Barraclough, Keith; Irvine, David, Data routing and management with routing path selectivity.
  8. Barraclough, Keith; Irvine, David, Device classification for media delivery.
  9. Marisetty,Suresh; Thangadurai,George; Ayyar,Mani, Error correction apparatus, systems, and methods.
  10. Barr,Andrew Harvey; Pomaranski,Ken Gary; Shidla,Dale John, Fault-tolerant multi-core microprocessing.
  11. Shaw, Mark, Hierarchy of fault isolation timers.
  12. Shaw, Mark, Hierarchy of fault isolation timers.
  13. Kracht, James, Identifying link failures in a network.
  14. Takahashi,Jin; Okada,Seishi, Information processing apparatus and error detecting method.
  15. Miller, Joseph P.; Olarig, Sompong P.; Stoddard, Donald J., Integrated circuit device/circuit board connection apparatus.
  16. Haydock,Steven, Interrupt handler for a data processor.
  17. Roden, Thomas; Shively, Darrell; Nguyen, Dan; Nadeau, Larry; Truong, Tina; Still, David N., Method and apparatus for managing a network using link state information.
  18. Ito,Masanao; Sakakibara,Tadayuki, Method for processing a diagnosis of a processor, information processing system and a diagnostic processing program.
  19. Aissi, Selim; Chhabra, Jasmeet; Prakash, Gyan, Method, apparatus and system for remote management of mobile devices.
  20. Govindarajalu,Hariprakash, Methods and apparatus for testing functionality of processing devices by isolation and testing.
  21. Hetherington, Ricky C.; Shah, Manish K.; Grohoski, Gregory F.; Saha, Bikram, Multiple-core processor with flexible mapping of processor cores to cache banks.
  22. Hetherington, Ricky C.; Saha, Bikram, Multiple-core processor with support for multiple virtual processors.
  23. Takeda, Kazumasa, Multiprocessor system for distributively determining the identity of a new control processor based upon the identity of the failing processor(s) stored therein.
  24. Kakadia, Deepak K., Network event correlation system using formally specified models of protocol behavior.
  25. Jesus A. Martinez ; Manoj B. Agnihotri, Power-on software for robust boot.
  26. Eisen, Susan Elizabeth; Le, Hung Qui; Mack, Michael James; Nguyen, Dung Quoc; Paredes, Jose Angel; Swaney, Scott Barnett, Processor instruction retry recovery.
  27. Eisen,Susan Elizabeth; Le,Hung Qui; Mack,Michael James; Nguyen,Dung Quoc; Paredes,Jose Angel; Swaney,Scott Barnett, Processor instruction retry recovery.
  28. Marisetty, Suresh; Thangadurai, George; Ayyar, Mani, Rendezvous of processors with OS coordination.
  29. Brown,Andrew, System and method of checking a computer system for proper operation.
  30. Nair, Sujith V.; Gingerich, Jamin L.; Desai, Tushar R.; Tomayko, Brian C., System monitor for monitoring functional modules of a system.
  31. Arabi,Tawfik; Ma,Hung Piao; Iovino,Gregory M.; Rotem,Shai; Kornfeld,Avner; Taylor,Gregory F., Testing arrangement to distribute integrated circuits.
  32. Prabhu,Manohar K., Testing processors.
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